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In this course, you will learn about the basic principles and current practices of computer architectures and organizations, including instruction set design, pipelining, caching, virtual memory, and parallelism. At the end of this course, you will understand how computers are organized and what influences have determined the architectures of processors, memory systems, and input/output systems. You will learn how to evaluate and improve computer system performance through design, analysis, and computer simulation. Finally, you will learn to read papers in the primary literature in support of materials found in the textbook.

Syllabus Schedule Reading List Architecture Research Seminar Series

Blackboard Handouts and Lecture Notes Assignments Related Links

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Announcements

• Starting on Tuesday 9/1/09 class will be in PAI 3.14 on TUESDAYS.
• Starting on Thursday 9/3/09 class will be in RAS 310 on THURSDAYS.
• The RISC paper review is due on Tuesday, September 15, at the beginning of class.
• Assignment 2 is due on Thursday, September 17, at the beginning of class.
• Starting on Thursday 9/17/09 class will be in RAS 312 on THURSDAYS.
• By popular vote, we will be maintaining our current classroom schedule for the remainder of the semester, barring unforeseen issues. So, PAI 3.14 on Tuesdays, and RAS 312 on Thursdays.
• Verilog tutorials and information on using the simulation tools are now available via the handouts section.
• Verilog tools are now working. Verilog homework assignment will be given out as HW 5 on October 1.
• Book Erratum - NVIDIA half precision and IEEE half precision are the same thing, meaning the exponent is in excess 15 format, not excess 16 as the book indicates. Please note this for homework 4.
• Midterm exam on Tuesday, October 20. It covers Chapters 1-4 in the text and the corresponding notes. There will be no questions on memory hierarchy. One of my old cs310 midterms and an old midterm from this course are both available on the schedule page.
• Project part (a) or HW 6 (Bug Hunt): There are eight bugs, not nine. The project statement has been updated accordingly. If you find a real ninth bug, that will be worth a bunch of extra credit ;-}
• A working but unpipelined Verilog version of the LC3.5 is available here.
• The final exam will be held on Wednesday December 9 from 2 to 5 in PAI 3.14 Pizza will be served. Dong will contact the class about pizza preference voting. The exam will be a midterm-level exam, focusing on material from chapters 5-7 in P&H. As usual, a page of notes will be allowed, as well as a calculator (okay, it can be programmable).
• Oh, and in spite of all your inspiring arguments, it will be a plain old exam, i.e. not optional or anything.

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