CS 352: Homework Assignment 4
      Assigned: Tuesday, February 23, 2010
      Due: Thursday, March 4, 2010 at the beginning of class
      Instructions: Show your work to receive full credit.

      • 4.2.1, 4.2.2, 4.2.3
      • 4.7.1, 4.7.2, 4.7.3
      • 4.7.X Which stage(s) limits execution time in a pipelined implementation with the given stage latencies?
      • 4.7.Y Which stages could be combined in a pipelined implementation without sacrificing latency?
      • 4.11.1, 4.11.2, 4.11.3
      • 4.13.1, 4.13.2, 4.13.3
      • 4.18.1, 4.18.2, 4.18.3



      Refer to program hw4.asm:

      1. What answer do you get by running the program? (i.e. what does this program compute)?
      2. What would happen if the branch instructions were actually delayed branch instructions?
      3. Rewrite the inner loop (between the labels loop and end) so that the program would in fact work with delayed branches. Can you do it without increasing the number of instructions in the inner loop?

      Recall from lecture that a delayed branch is one that does not take effect until one instruction later than you would otherwise expect.