Research

	Interests:		Computer architecture, reconfigurable logic, computing technologies, ubiquitous and wearable computing, privacy and personal data management, mobile devices, cloud services, datacenter designs, and optimizing compilers.
	Research:		2011-2016: Catapult, deploying reconfigurable logic at large scale in the cloud. Three other projects not yet public. 2008-2011: Computer Architecture Group at MSR, Redmond Lab (focus on personal data services and phase-change memory) 2000-2008: The TRIPS project in the Computer Architecture and Technology Laboratory aka CART).

Selected publications

(Full list of publications on my resume / CV). A Configurable Cloud-Scale DNN Processor for Real-Time AI (ISCA-18) Azure Accelerated Networking: SmartNICs in the Public Cloud (NSDI-18) A Cloud-Scale Acceleration Architecture (MICRO-16) A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services (ISCA-14) General-Purpose Code Acceleration with Limited-Precision Analog Computation (ISCA-14) How To Implement Effective Prediction and Forwarding for Fusable Dynamic Multicore Architectures (HPCA-13) Neural Acceleration for General-Purpose Approximate Programs (MICRO-12) Dark Silicon and the End of Multicore Scaling (ISCA-11) Pocket Cloudlets (ASPLOS-11) Better I/O Through Byte-Addressable, Persistent Memory (SOSP-09) Architecting Phase-Change Memory as a Scalable DRAM Alternative (ISCA-09) An Evaluation of the TRIPS Computer System (ASPLOS-09) Strategies for Mapping Dataflow Blocks to Distributed Hardware (MICRO-08) Composable Lightweight Processors (MICRO-07) Late Binding: Enabling Unordered Load-Store Queues (ISCA-07) A NUCA Substrate for Flexible CMP Cache Sharing (ICS-05) Scaling to the End of Silicon with EDGE Architectures (IEEE Computer, July '04) Scalable Hardware Memory Disambiguation for High-ILP Processors (MICRO-03) An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches (ASPLOS-02) Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic (DSN-02) The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays (ISCA-02) Clock Rate versus IPC: the End of the Road for Conventional Microarchitectures (ISCA-00)

CART Alums:

Ph.D.

Dong Li, May 2014 Dissertation: "Orchestrating Thread Scheduling and Cache Management to Improve Memory System Throughput in Throughput Processors" First employment: Senior Engineer, Qualcomm Research, Qualcomm Corporation, Santa Clara, CA. Renee St. Amant, May 2014 Dissertation: "Enabling High-Performance, Mixed-Signal Approximate Computing" First employment: Author Hadi Esmaeilzadeh, May 2013 Dissertation: "Approximate Acceleration for a Post-Multicore Era" First employment: Assistant Professor, College of Computing, Georgia Tech, Atlanta, GA. Behnam Robatmili, August 2011 Dissertation: "Efficient Execution of Sequential Applications on Multicore Systems" First employment: Senior Engineer, Qualcomm Research, Qualcomm Corporation, Santa Clara, CA. Bert Maher, August 2010 Dissertation: "Atomic Block Formation for Explicit Data Graph Execution Architectures" First employment: Software Engineer, Intel Corporation, Santa Clara, CA. Aaron Smith, December 2009 Dissertation: "Explicit Data Graph Compilation" First employment: Research Software Design Engineer, Microsoft Research, Redmond, WA. Haiming Liu, March 2009 Dissertation: "Hardware Techniques to Improve Cache Efficiency" First employment: Senior Design Engineer, Advanced Micro Devices, Austin, TX. Nitya Ranganathan, February 2009 Dissertation: "Control Flow Speculation for Distributed Architectures" First employment: Senior Design Engineer, Advanced Micro Devices Research and Development Lab, Austin, TX. Simha Sethumadhavan, August 2007 Dissertation: "Scalable Hardware Memory Disambiguation" First employment: Assistant Professor, Department of Computer Science, Columbia University, New York, NY. Changkyu Kim, July 2007 Dissertation: "A Technology Scalable Composable Architecture" First employment: Research Scientist, Intel Corporation, Santa Clara, CA. Ramadass Nagarajan, May 2007 Dissertation: "Design and Evaluation of a Technology-Scalable Architecture for Instruction-Level Parallelism" First employment: Platform Architect, Intel Corporation, Portland, OR. Karu Sankaralingam, November 2006 (principal advisor: Steve Keckler) Dissertation: "Polymorphous Architectures: A Unified Approach for Extracting Concurrency of Different Granularities" First employment: Computer Sciences Department, University of Wisconsin-Madison, Madison, WI. Jaehyuk Huh, May 2006 Dissertation: "Hardware Techniques to Reduce Communication Costs in Multiprocessors" First employment: Senior Design Engineer, Advanced Micro Devices, Sunnyvale, CA. Rajagopalan Desikan, December 2005 Dissertation: "Distributed Selective Re-Execution for EDGE Architectures" First employment: Senior Design Engineer, Advanced Micro Devices, Austin, TX. M.S. Hrishikesh, July 2004 Dissertation: "Design of Wide-Issue High-Frequency Processors in Wire-Delay Dominated Technologies" First employment: Senior Component Design Engineer, Intel, Folsom, CA. Vikas Agarwal, May 2004 (principal advisor: Steve Keckler) Dissertation: "Scalable Primary Cache Memory Architectures" First employment: Advisory Engineer, International Business Machines, Austin, TX.

B.S.

Franzi Roesner Honors Undergraduate Thesis: "Counting Dependence Predictors" First employment: Ph.D. program in Computer Sciences and Engineering, University of Washington Kevin Bush First employment: M.S. program in Computer Sciences, The University of Texas at Austin Jacob Leverich First employment: Ph.D. program in Computer Sciences, Stanford University Yasuko Watanabe First employment: Ph.D. program in Computer Sciences, University of Wisconsin-Madison Luke Yen First employment: Ph.D. program in Computer Sciences, University of Wisconsin-Madison

Miscellanea

UT Computer Architecture Seminar Faculty advisor for the UT Marathon team (2002 team pic)