The MIR representation corresponds to the operations available on a modern microprocessor. There are three major assumptions underlying this statement.
First, we assume that we are generating code for a load-store RISC-type processor. This assumption guides the selection of the basic addressable memory location used in operations.
Second, we assume that the architecture supports a register indirect with offset addressing mode; if the base address of an array or structure is loaded in a register, we can load the value from the proper offset location in a single instruction.2
Third, we assume that the instruction set architecture (ISA) supports moving values from a condition register(s) into a general-purpose register. This assumption allows us to leave assignments where the right-hand side uses a relational operator. To determine the value of the assignment, we can use shifting, masking, and inverting to extract the relevant bit from the condition register value.