CS 352H Verilog Page

CS 352H Verilog Info

Before you start...

Log into a department Linux machine. For details on available machines check the department compute facilities web page.
Set up your environment, refer to the environment setup page.

Simulation

We will be using simulation for functional testing and verification of the verilog code.
The VCS simulation tool will be used for all testing and simulation cs352h.

VCS Documentation
- The full VCS documentation may be found at: /projects/cad/synopsys/vcs/vcs-mx_vX-2005.06-SP2/doc/
  In particular the vcsmx_ug.pdf (VCS User Guide) and the vcsmxqr.pdf (VCS Quick Reference Guide) may be useful.
  (note: these links will only work from CS unix machines)

Verilog HDL

Verilog HDL is a functional verification and simulation language for digital systems. There are many sources of information available on the web for verilog, here are a few highlights:

Simple combinatorial verilog tutorial presented in cs310h some years ago.
Second tutorial covering sequential logic, delay modeling and tristates.
Third tutorial covering control logic.

ASIC World verilog tutorial.
AMBIT Design System's Verilog HDL quick reference
Dr. Daniel C. Hyde at Bucknell University's Handbook on Verilog HDL
The "Alternate" Verilog FAQ
Google Groups: comp.lang.verilog archives

There is a free (GPL'ed) verilog mode for emacs available at verilog.com. It can be extremely useful for those that use emacs as their primary editor. It has auto indentation, context sensitive colored highlighting, signal and command completion as well as pre-processor type functions.

Last modified: 10/13/09 by Don Fussell fussell@cs.utexas.edu