Generate a module that XORs a bit with each bit of a vector.
(vl-make-n-bit-xor-each n) → mods
We generate a module that uses gates and is semantically equivalent to:
module VL_N_BIT_XOR_EACH (out, a, b) output [n-1:0] out; input a; input [n-1:0] b; assign out[0] = a ^ b[0]; ... assign out[n-1] = a ^ b[n-1]; endmodule
In other words, we xor
Function:
(defun vl-make-n-bit-xor-each (n) (declare (xargs :guard (posp n))) (declare (xargs :guard t)) (let ((__function__ 'vl-make-n-bit-xor-each)) (declare (ignorable __function__)) (b* ((n (lposfix n)) (name (hons-copy (cat "VL_" (natstr n) "_BIT_XOR_EACH"))) ((mv out-expr out-port out-portdecl out-vardecl) (vl-occform-mkport "out" :vl-output n)) ((mv a-expr a-port a-portdecl a-vardecl) (vl-occform-mkport "a" :vl-input 1)) ((mv b-expr b-port b-portdecl b-vardecl) (vl-occform-mkport "b" :vl-input n)) (a-wires (replicate n a-expr)) (b-wires (vl-make-list-of-bitselects b-expr 0 (- n 1))) (out-wires (vl-make-list-of-bitselects out-expr 0 (- n 1))) (insts (vl-simple-inst-list *vl-1-bit-xor* "bit" out-wires a-wires b-wires))) (list (make-vl-module :name name :origname name :ports (list out-port a-port b-port) :portdecls (list out-portdecl a-portdecl b-portdecl) :vardecls (list out-vardecl a-vardecl b-vardecl) :modinsts insts :minloc *vl-fakeloc* :maxloc *vl-fakeloc*)))))
Theorem:
(defthm vl-modulelist-p-of-vl-make-n-bit-xor-each (b* ((mods (vl-make-n-bit-xor-each n))) (vl-modulelist-p mods)) :rule-classes :rewrite)
Theorem:
(defthm type-of-vl-make-n-bit-xor-each (and (true-listp (vl-make-n-bit-xor-each n)) (consp (vl-make-n-bit-xor-each n))) :rule-classes :type-prescription)
Theorem:
(defthm vl-make-n-bit-xor-each-of-pos-fix-n (equal (vl-make-n-bit-xor-each (pos-fix n)) (vl-make-n-bit-xor-each n)))
Theorem:
(defthm vl-make-n-bit-xor-each-pos-equiv-congruence-on-n (implies (acl2::pos-equiv n n-equiv) (equal (vl-make-n-bit-xor-each n) (vl-make-n-bit-xor-each n-equiv))) :rule-classes :congruence)