One-bit division and remainder.
This module exactly implements the Verilog semantics for one-bit division and remainder.
Dividing one-bit wires isn't a very useful thing to do. Division by zero is
generally an error (in Verilog it produces X), and division by one is just a
copy. But, if for some reason we do see a
The actual definition of this module is pretty weird and I don't think it's really worth studying. I basically just piled on X detection stuff until it matched the Verilog semantics.
Definition:
(defconst *vl-1-bit-div-rem* (b* ((name (hons-copy "VL_1_BIT_DIV_REM")) ((mv q-expr q-port q-portdecl q-vardecl) (vl-primitive-mkport "quotient" :vl-output)) ((mv r-expr r-port r-portdecl r-vardecl) (vl-primitive-mkport "remainder" :vl-output)) ((mv e-expr e-port e-portdecl e-vardecl) (vl-primitive-mkport "dividend" :vl-input)) ((mv d-expr d-port d-portdecl d-vardecl) (vl-primitive-mkport "divisor" :vl-input)) ((mv xwire-expr xwire-vardecl) (vl-primitive-mkwire "xwire")) (xwire-inst (vl-simple-inst *vl-1-bit-x* "xdriver" xwire-expr)) ((mv d~-expr d~-vardecl) (vl-primitive-mkwire "divisor_bar")) ((mv dx-expr dx-vardecl) (vl-primitive-mkwire "divisor_x")) ((mv df-expr df-vardecl) (vl-primitive-mkwire "divisor_fix")) (d~-inst (vl-simple-inst *vl-1-bit-not* "dx1" d~-expr d-expr)) (dx-inst (vl-simple-inst *vl-1-bit-and* "dx2" dx-expr d~-expr xwire-expr)) (df-inst (vl-simple-inst *vl-1-bit-or* "dx3" df-expr d-expr dx-expr)) ((mv xa-expr xa-vardecl) (vl-primitive-mkwire "xa")) ((mv xb-expr xb-vardecl) (vl-primitive-mkwire "xb")) (xa-inst (vl-simple-inst *vl-1-bit-xor* "x1" xa-expr e-expr e-expr)) (xb-inst (vl-simple-inst *vl-1-bit-xor* "x2" xb-expr df-expr df-expr)) (r-inst (vl-simple-inst *vl-1-bit-xor* "x3" r-expr xa-expr xb-expr)) ((mv qm-expr qm-vardecl) (vl-primitive-mkwire "qmain")) (qm-inst (vl-simple-inst *vl-1-bit-and* "q1" qm-expr e-expr df-expr)) (q-inst (vl-simple-inst *vl-1-bit-xor* "q2" q-expr r-expr qm-expr))) (hons-copy (make-vl-module :name name :origname name :ports (list q-port r-port e-port d-port) :portdecls (list q-portdecl r-portdecl e-portdecl d-portdecl) :vardecls (list q-vardecl r-vardecl e-vardecl d-vardecl xwire-vardecl d~-vardecl dx-vardecl df-vardecl xa-vardecl xb-vardecl qm-vardecl) :modinsts (list xwire-inst d~-inst dx-inst df-inst xa-inst xb-inst r-inst qm-inst q-inst) :minloc *vl-fakeloc* :maxloc *vl-fakeloc*))))