Degenerate 1-bit dynamic bit-selection module.
The module
module VL_1_BIT_DYNAMIC_BITSELECT (out, in, idx); output out; input in; input idx; wire idx_bar; wire a; wire b; not(idx_bar, idx); and(a, idx_bar, in); and(b, idx, 1'bx); or(out, a, b); endmodule
Definition:
(defconst *vl-1-bit-dynamic-bitselect* (b* ((name (hons-copy "VL_1_BIT_DYNAMIC_BITSELECT")) ((mv out-expr out-port out-portdecl out-vardecl) (vl-primitive-mkport "out" :vl-output)) ((mv in-expr in-port in-portdecl in-vardecl) (vl-primitive-mkport "in" :vl-input)) ((mv idx-expr idx-port idx-portdecl idx-vardecl) (vl-primitive-mkport "idx" :vl-input)) ((mv ~idx-expr ~idx-vardecl) (vl-primitive-mkwire "idx_bar")) ((mv a-expr a-vardecl) (vl-primitive-mkwire "a")) ((mv b-expr b-vardecl) (vl-primitive-mkwire "b")) (~idx-inst (vl-simple-inst *vl-1-bit-not* "mk_idx_bar" ~idx-expr idx-expr)) (a-inst (vl-simple-inst *vl-1-bit-and* "mk_a" a-expr ~idx-expr in-expr)) (b-inst (vl-simple-inst *vl-1-bit-and* "mk_b" b-expr idx-expr |*sized-1'bx*|)) (out-inst (vl-simple-inst *vl-1-bit-or* "mk_out" out-expr a-expr b-expr))) (hons-copy (make-vl-module :name name :origname name :ports (list out-port in-port idx-port) :portdecls (list out-portdecl in-portdecl idx-portdecl) :vardecls (list out-vardecl in-vardecl idx-vardecl ~idx-vardecl a-vardecl b-vardecl) :modinsts (list ~idx-inst a-inst b-inst out-inst) :minloc *vl-fakeloc* :maxloc *vl-fakeloc*))))