One-bit multiplier.
This module implements a one-bit multiply. Normally you would
think of this as an
The actual Verilog definition of this module is as follows. These gates
precisely implement the Verilog semantics for
module VL_1_BIT_MULT (o, a, b); output o; input a, b; wire p0, x0, x1; and (p0, a, b); xor (x0, a, b); xor (x1, x0, x0); xor (o, p0, x1); endmodule
Definition:
(defconst *vl-1-bit-mult* (b* ((name (hons-copy "VL_1_BIT_MULT")) ((mv o-expr o-port o-portdecl o-vardecl) (vl-primitive-mkport "o" :vl-output)) ((mv a-expr a-port a-portdecl a-vardecl) (vl-primitive-mkport "a" :vl-input)) ((mv b-expr b-port b-portdecl b-vardecl) (vl-primitive-mkport "b" :vl-input)) ((mv p0-expr p0-vardecl) (vl-primitive-mkwire "p0")) ((mv x0-expr x0-vardecl) (vl-primitive-mkwire "x0")) ((mv x1-expr x1-vardecl) (vl-primitive-mkwire "x1")) (p0-inst (vl-simple-inst *vl-1-bit-and* "mk_p0" p0-expr a-expr b-expr)) (x0-inst (vl-simple-inst *vl-1-bit-xor* "mk_x0" x0-expr a-expr b-expr)) (x1-inst (vl-simple-inst *vl-1-bit-xor* "mk_x1" x1-expr x0-expr x0-expr)) (o-inst (vl-simple-inst *vl-1-bit-xor* "mk_o" o-expr p0-expr x1-expr))) (hons-copy (make-vl-module :name name :origname name :ports (list o-port a-port b-port) :portdecls (list o-portdecl a-portdecl b-portdecl) :vardecls (list o-vardecl a-vardecl b-vardecl p0-vardecl x0-vardecl x1-vardecl) :modinsts (list p0-inst x0-inst x1-inst o-inst) :minloc *vl-fakeloc* :maxloc *vl-fakeloc*))))