Parse a
(vl-parse-concurrent-assertion-statement &key (tokstream 'tokstream) (config 'config)) → (mv errmsg? value new-tokstream)
Almost the SystemVerilog-2012 grammar:
concurrent_assertion_statement ::= assert_property_statement | assume_property_statement | cover_property_statement | cover_sequence_statement | restrict_property_statement assert_property_statement ::= 'assert' 'property' '(' property_spec ')' action_block assume_property_statement ::= 'assume' 'property' '(' property_spec ')' action_block cover_property_statement ::= 'cover' 'property' '(' property_spec ')' statement_or_null cover_sequence_statement ::= 'cover' 'sequence' '(' property_spec ')' statement_or_null restrict_property_statement::= 'restrict' 'property' '(' property_spec ')' ';'
The real grammar doesn't use a