Well-formedness
Sanity checks for the well-formedness of Verilog modules.
Subtopics
- Defwellformed
- Defwellformed is a macro for introducing well-formedness
checking functions.
- Reasonable
- Identify modules in our supported subset of Verilog.
- Lvaluecheck
- Checks to ensure that expressions used in lvalue positions are valid
in the sense of vl-expr-lvaluep.
