Primitives
The primitive modules targetted by VL.
The modules here can sort of be thought of as the target language
for VL's simplification scheme. That is, the sequence of transforms
applied by vl-simplify tries to convert rich Verilog modules that
include expressions, gates, parameters, etc., into simple, hierarchical modules
that do nothing more than instantiate other modules, with these primitive
modules at the tips.
This set of primitives modules could be simplified. For instance we could
rewrite all of the basic gate modules into nand or some other basic form.
We haven't done this yet, under the (probably misguided) theory that having a
richer set of primitives might somehow be more efficient for our symbolic
simulator.
Note that the list below is somewhat incomplete. For instance, in
the final e-conversion step, we can generate "resolution" modules for
resolving multiple drivers. These resolution modules are essentially
primitives. But there isn't a fixed set of resolution primitives, instead we
generate the primitives we need on the fly; see vl-make-n-bit-res-module, for instance.
Similarly, historically VL had a single VL_1_BIT_FLOP primitive, but
when we added support for always blocks with multiple edge triggers, we
did away with this. Instead, VL can now generate many kinds of primitive
flops, each with a supporting E module. See, e.g., vl-make-1-bit-n-edge-flop.
Subtopics
- *vl-1-bit-approx-mux*
- Primitive 1-bit (more conservative) multiplexor module.
- *vl-1-bit-mux*
- Primitive 1-bit (less conservative) multiplexor module.
- Nedgeflop
- Generation of new primitives for edge-triggered always
blocks.
- Vl-primitive-mkport
- Convenient way to generate a port for a primitive.
- *vl-1-bit-assign*
- Primitive assignment module.
- *vl-1-bit-zmux*
- Primitive tri-state buffer module.
- Vl-primitive-mkwire
- Convenient way to generate an internal wire for a primitive.
- *vl-1-bit-bufif1*
- Primitive conditional driver.
- *vl-1-bit-bufif0*
- Primitive conditional driver.
- *vl-1-bit-delay-1*
- Primitive assignment with delay.
- *vl-1-bit-ceq*
- Primitive === module.
- *vl-1-bit-buf*
- Primitive buffer module.
- *vl-1-bit-rcmos*
- Primitive resistive cmos transistor.
- *vl-1-bit-latch*
- Primitive level-sensitive latch.
- *vl-1-bit-cmos*
- Primitive cmos transistor.
- *vl-1-bit-power*
- Primitive power source or supply1 signal.
- *vl-1-bit-rpmos*
- Primitive resistive pmos transistor.
- *vl-1-bit-rnmos*
- Primitive resistive nmos transistor.
- *vl-1-bit-pmos*
- Primitive pmos transistor.
- *vl-1-bit-nmos*
- Primitive nmos transistor.
- *vl-1-bit-ground*
- Primitive ground or supply0 signal.
- *vl-1-bit-tranif1*
- Primitive, conditional bidirectional connection.
- *vl-1-bit-tranif0*
- Primitive, conditional bidirectional connection.
- *vl-1-bit-rtranif1*
- Primitive, resistive, conditional bidirectional connection.
- *vl-1-bit-rtranif0*
- Primitive, resistive, conditional bidirectional connection.
- *vl-1-bit-rtran*
- Primitive, resistive bidirectional connection.
- *vl-1-bit-tran*
- Primitive bidirectional connection.
- *vl-1-bit-notif1*
- Primitive conditional driver.
- *vl-1-bit-notif0*
- Primitive conditional driver.
- *vl-1-bit-and*
- Primitive and-gate module.
- *vl-1-bit-xor*
- Primitive xor-gate module.
- *vl-1-bit-xnor*
- Primitive xnor-gate module.
- *vl-1-bit-pullup*
- Primitive pullup element.
- *vl-1-bit-pulldown*
- Primitive pulldown element.
- *vl-1-bit-or*
- Primitive or-gate module.
- *vl-1-bit-not*
- Primitive not-gate module.
- *vl-1-bit-nor*
- Primitive nor-gate module.
- *vl-1-bit-nand*
- Primitive nand-gate module.
- *vl-1-bit-z*
- Primitive Z (floating) generator.
- *vl-1-bit-x*
- Primitive X (unknown) generator.
- *vl-1-bit-t*
- Primitive 1 (true) generator.
- *vl-1-bit-f*
- Primitive 0 (false) generator.
