Parser
A parser for a subset of Verilog and SystemVerilog.
Introduction
Our parser is responsible for processing a list of tokens into our
internal representation of Verilog syntax. Typically these tokens are
produced by the lexer. Note that before parsing begins, any whitespace
or comment tokens should be removed from the token list; see for instance vl-kill-whitespace-and-comments.
We use essentially a manual recursive-descent style parser. Having the
entire token stream available gives us arbitrary lookahead, and we occasionally
make use of backtracking.
Scope
Verilog and SystemVerilog are huge languages, and we can parse only a subset
of these languages.
We can currently support most of the constructs in the Verilog 1364-2005
standard. Notably, we do not yet support user-defined primitives, generate
statements, specify blocks, specparams, and genvars. In some cases, the parser
will just skip over unrecognized constructs (adding warnings when it
does so.) Depending on what you are doing, this behavior may be actually
appropriate, e.g., skipping specify blocks may be okay if you aren't trying to
deal with low-level timing issues.
We are beginning to work toward supporting SystemVerilog based on the
1800-2012 standard. But this is preliminary work and you should not yet expect
VL to correctly handle any interesting fragment of SystemVerilog.
Subtopics
- Parse-expressions
- Parser for Verilog and SystemVerilog expressions.
- Parse-udps
- Functions for parsing User Defined Primitives (UDPs).
- Parse-statements
- Functions for parsing Verilog and SystemVerilog procedural statements.
- Parse-property
- Functions for parsing SystemVerilog assertion sequence and property
expressions.
- Vl-genelements
- Parser for elements contained within modules, interfaces, etc., including
generate constructs.
- Parse-paramdecls
- Functions for parsing parameter declarations.
- Parse-blockitems
- Functions for parsing Verilog and SystemVerilog block items.
- Parse-utils
- Supporting functions for the parser.
- Parse-insts
- Functions for parsing module instances.
- Parse-functions
- Functions for parsing Verilog-2005 and SystemVerilog function and
task declarations.
- Parse-assignments
- Functions for parsing lvalue expressions and assignments.
- Parse-clocking
- Functions for parsing SystemVerilog clocking blocks.
- Parse-strengths
- Functions for parsing drive/charge strengths.
- Vl-parse-genvar-declaration
- Match genvar_declaration.
- Vl-parse
- Top level parsing function.
- Parse-netdecls
- Functions for parsing net declarations.
- Parse-asserts
- Functions for parsing SystemVerilog assertions.
- Vl-maybe-parse-lifetime
- Match an optional lifetime for SystemVerilog-2012.
- Parse-dpi-import-export
- Functions for parsing DPI import/export statements.
- Parse-ports
- Functions for parsing Verilog and SystemVerilog ports.
- Parse-timeunits
- Functions for parsing SystemVerilog timeunit and
timeprecision declarations.
- Seq
- A variant of ACL2::seq for use in VL's parser.
- Parse-packages
- Functions for parsing SystemVerilog packages.
- Parse-eventctrl
- Functions for parsing event controls.
