Vl-vardecl
Representation of a single variable or net (e.g., wire) declaration.
This is a product type introduced by defprod.
Fields
- name — stringp
- Name of the variable being declared.
- loc — vl-location
- Where the declaration was found in the source code.
- type — vl-datatype
- Data type, array dimensions. See below.
- nettype — vl-maybe-nettypename
- Net type (i.e., resolution function, distinct from datatype) or
nil if this a reg or variable instead of a net. See
below.
- atts — vl-atts
- Any attributes associated with this declaration.
- initval — vl-maybe-rhs
- (Variables only). When present, indicates the initial value for
the variable, e.g., for integer i = 3; the initval will
be the vl-expr-p for 3. Note that when net
declarations have initial values, the parser turns them into
separate continuous assignment statements, instead.
- constp — booleanp
- (Variables only). Indicates whether the const keyword was
provided.
- constval — sv::maybe-4vec
- If the const keyword was given, we try and resolve the ~
initval to a constant. If successful, we store that value ~
here.
- varp — booleanp
- (Variables only). Indicates whether the var keyword was
provided.
- lifetime — vl-lifetime-p
- (Variables only). See SystemVerilog-2012 Section 6.21. There
are pretty complex rules for variable lifetimes. BOZO we don't
really support this yet in any meaningful way, and the
lifetime field is currently just used to record whether a
static or automatic keyword was found during parsing.
- vectoredp — booleanp
- (Nets only) True if the vectored keyword was explicitly
provided. See SystemVerilog-2012 section 6.9.2. This flag is
rather obscure and appears to have something to do with whether
the net will be ``expanded'' for the purposes of the Verilog
Programming Language Interface (PLI). Vectored nets should
apparently not be bit- or part-selected from and should not
have strengths. This does not seem particularly relevant to
anything and VL generally ignores this flag.
- scalaredp — booleanp
- (Nets only) True if the scalared keyword was explicitly
provided. See SystemVerilog-2012 section 6.9.2. Again this is
not well specified and probably irrelevant. VL generally
ignores this.
- delay — vl-maybe-gatedelay
- (Nets only) The delay associated with this wire, if any.
For instance, wire #1 foo has a delay of 1, and means that
it takes 1 time unit for the net to change its value in
response to a change on any driver (Verilog-2005, 7.14). The
default delay is zero when no delay is specified, but we
represent the delay using a vl-maybe-gatedelay-p, and
use NIL when no delay is specified. Note per
Verilog-2005, Section 6.1.3, that when a delays is provided in
the combined declaration and assignment statement like wire
#10 a = 1, b = 2, then the delay is associated with each
assignment and not with the net declaration for a;
see vl-assign-p for more information.
- cstrength — vl-maybe-cstrength
- (Trireg nets only). The charge strength associated with the
net, if any. For instance, trireg medium foo will have a
cstrength of medium; the cstrength will be
nil for all non-trireg nets, regs, and variables; it will
also be nil for trireg nets that do not explicitly
give a charge strength.
Verilog-2005 and SystemVerilog-2012 distinguish between nets and
variables. For example:
wire signed [4:0] w; // net
supply1 vdd; // net
wand [3:0] a; // net
reg [4:0] r; // variable
logic signed [1:0] l; // variable
integer i; // variable
mybus_t b; // variable
In early versions of VL, we also separated nets from variables in
our internal representation of Verilog syntax. However, we
eventually decided that merging together these concepts into a single
representation would be simpler. Today, we use the same
vl-vardecl structures to represent:
- net declarations,
- reg declarations, and
- all other variable declarations (e.g., logic,
mystruct_t, etc.)
Any of these declarations introduces a named entity that has
certain properties. Some of these properties, like its dimension(s)
and whether it is regarded as signed, are captured by the notion of a
SystemVerilog variable type or data type. We represent
this information as an ordinary vl-datatype, found in the
type field of the vl-vardecl.
The main difference between nets and datatypes is that nets can be
used with multiple drivers. To support resolving multiple drivers in
different ways, net declarations can include a net type such as
wire for plain wires, wor for a wired or, supply0 for a
ground wire, and similar. Despite its name, the ``net type''
has nothing to do with the ordinary notion of a data type! (This
terminology, unfortunately, comes from the Verilog/SystemVerilog
standards; see for instance SystemVerilog-2012 section 6.5).
Here are some examples of basic net declarations.
module m (a, b, c) ;
wire [4:0] w ; // <-- plain net declaration
wire ab = a & b ; // <-- net declaration with assignment
...
endmodule
Net declarations can also arise from using the combined form of
port declarations.
module m (a, b, c) ;
input wire a; // <-- net declaration in a port declaration
...
endmodule
They can also arise from the more modern ANSI style ports, e.g.,
module m (input wire a, ...) ;
You can also string together net declarations, e.g., by writing
wire w1, w2;. In all of these cases, our parser generates
a separate vl-vardecl-p object for each declared wire. When an
assignment is also present, the parser creates a corresponding,
separate vl-assign-p object to contain the assignment. Hence,
each vl-vardecl-p really and truly only represents a single
declaration. Similarly, combined variable declarations such as
"integer a, b" are split apart into multiple, individual
declarations.
Subtopics
- Vl-vardecl-p
- Recognizer for vl-vardecl structures.
- Vl-vardecl-fix
- Fixing function for vl-vardecl structures.
- Make-vl-vardecl
- Basic constructor macro for vl-vardecl structures.
- Vl-vardecl-equiv
- Basic equivalence relation for vl-vardecl structures.
- Change-vl-vardecl
- Modifying constructor for vl-vardecl structures.
- Vl-vardecl->nettype
- Get the nettype field from a vl-vardecl.
- Vl-vardecl->cstrength
- Get the cstrength field from a vl-vardecl.
- Vl-vardecl->vectoredp
- Get the vectoredp field from a vl-vardecl.
- Vl-vardecl->scalaredp
- Get the scalaredp field from a vl-vardecl.
- Vl-vardecl->name
- Get the name field from a vl-vardecl.
- Vl-vardecl->lifetime
- Get the lifetime field from a vl-vardecl.
- Vl-vardecl->initval
- Get the initval field from a vl-vardecl.
- Vl-vardecl->delay
- Get the delay field from a vl-vardecl.
- Vl-vardecl->constval
- Get the constval field from a vl-vardecl.
- Vl-vardecl->constp
- Get the constp field from a vl-vardecl.
- Vl-vardecl->varp
- Get the varp field from a vl-vardecl.
- Vl-vardecl->type
- Get the type field from a vl-vardecl.
- Vl-vardecl->loc
- Get the loc field from a vl-vardecl.
- Vl-vardecl->atts
- Get the atts field from a vl-vardecl.
