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• Syntax

Statements

Representation of a statement.

Verilog includes a number of statements for behavioral modelling. Some of these (assignments, event triggers, enables and disables) are atomic in that they do not contain any sub-statements. We call the other statements (loops, cases, if statements, etc.) compound since they contain sub-statements and are mutually-recursive with vl-stmt-p.

Subtopics

Vl-stmt

Vl-cassertion

Representation of a concurrent assertion.

Vl-assertion

Representation of an immediate assertion.

Vl-stmtlist

A list of vl-stmt-p objects.

Vl-caselist

An alist mapping vl-exprlist-p to vl-stmt-p.