Vl-clkassign
Representation of a single clocking assignment (clocking blocks).
This is a product type introduced by defprod.
Fields
- name — stringp
- Name of the wire being sampled or expression being named.
- loc — vl-location
- Location of this clocking assignment.
- inputp — booleanp
- Indicates whether this is an input or output clocking
variable. See below for notes on inouts.
- rhs — vl-maybe-expr
- Expression to sample, or nil if there is no such expression.
When provided, this might typically be a hierarchical reference to
some signal, but it could also be something more complex like a
concatenation.
- skew — vl-maybe-clkskew
- Clock skew for when to sample this variable, if specified.
Some examples:
clocking @(posedge clk);
input #3 foo; // <-- clkassign with delay and no rhs
output bar = top.sub.mybar; // <-- clkassign with an rhs
inout baz; // <-- two clkassigns, one input, one output
endclocking
The SystemVerilog-2012 grammar allows inouts here, but note
from Section 14.1 (page 303) that ``a clockvar whose
clocking_direction is inout shall behave as if it were two clockvars,
one input and one output, having the same name and same
clocking_signal.'' We take this approach in VL: when the parser
encounters an inout, we explicitly split it up into separate
input/output clkassigns.
Subtopics
- Vl-clkassign-fix
- Fixing function for vl-clkassign structures.
- Vl-clkassign-equiv
- Basic equivalence relation for vl-clkassign structures.
- Vl-clkassign-p
- Recognizer for vl-clkassign structures.
- Make-vl-clkassign
- Basic constructor macro for vl-clkassign structures.
- Vl-clkassign->skew
- Get the skew field from a vl-clkassign.
- Vl-clkassign->rhs
- Get the rhs field from a vl-clkassign.
- Vl-clkassign->inputp
- Get the inputp field from a vl-clkassign.
- Change-vl-clkassign
- Modifying constructor for vl-clkassign structures.
- Vl-clkassign->name
- Get the name field from a vl-clkassign.
- Vl-clkassign->loc
- Get the loc field from a vl-clkassign.
