Representation of strengths for a assignment statements, gate instances, and module instances.
This is a product type introduced by defprod.
WARNING. We have not paid much attention to strengths, and our transformations probably do not handle them properly.
See sections 7.1.2 and 7.9 of the Verilog-2005 standard for discussion of strength modelling. Every regular gate has, associated with it, two drive strengths; a "strength0" which says how strong its output is when it is a logical zero, and "strength1" which says how strong the output is when it is a logical one. Strengths also seem to be used on assignments and module instances.
There seem to be some various rules for default strengths in 7.1.2, and also in 7.13. But our parser does not try to implement these defaults, and we only associate strengths onto module items where they are explicitly specified.