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Syntax

Vl-initial

Representation of an initial statement.

This is a product type introduced by defprod.

Fields

stmt — vl-stmt: Represents the actual statement, e.g., r = 0 below.
atts — vl-atts: Any attributes associated with this initial block.
loc — vl-location: Where the initial block was found in the source code.

Initial statements in Verilog are used to set up initial values for simulation. For instance,

module mymod (a, b, ...) ;
  reg r, s;
  initial r = 0;   <-- initial statement
endmodule

BOZO Our plan is to eventually generate initial statements from register and variable declarations with initial values, i.e., reg r = 0;.

Subtopics

Vl-initial-fix: Fixing function for vl-initial structures.
Vl-initial-p: Recognizer for vl-initial structures.
Vl-initial-equiv: Basic equivalence relation for vl-initial structures.
Make-vl-initial: Basic constructor macro for vl-initial structures.
Vl-initial->loc: Get the loc field from a vl-initial.
Vl-initial->atts: Get the atts field from a vl-initial.
Change-vl-initial: Modifying constructor for vl-initial structures.
Vl-initial->stmt: Get the stmt field from a vl-initial.