Nedgeflop
Generation of new primitives for edge-triggered always
blocks.
See edgesynth for an overview of how we handle edge-triggered
always blocks.
To support these blocks, VL creates primitive flip-flop modules with some
number of edges. For instance, the primitive 3-edge flop can be described as
follows in Verilog, and could be used to implement a flip-flop with, e.g.,
asynchronous set and reset signals.
module VL_1_BIT_3_EDGE_FLOP (q, d0, d1, d2, clk0, clk1, clk2);
output reg q;
input d0, d1, d2;
input clk0, clk1, clk2;
always @(posedge clk0 or posedge clk1)
if (clk0)
q <= d0
else if (clk1)
q <= d1;
else
q <= d2;
endmodule
The functions below generate these primitive modules and their corresponding
esim implementations.
Subtopics
- Vl-make-same-bitselect-from-each
- (vl-make-same-bitselect-from-each x index) maps vl-make-bitselect across a list.
- Vl-primitive-mkports
- Helper function for creating lists of primitive port declarations.
- Vl-nedgeflop-ifstmt
- Build the Verilog if-statement for a primitive n-edge flop.
- Vl-make-1-bit-n-edge-flop
- Build the primitive VL module for an n-edge flop.
- Vl-make-nedgeflop-insts
- Vl-nedgeflop-always
- Build the Verilog always statement for a primitive n-edge flop.
- Vl-nedgeflop-clkedge-assigns
- Vl-nedgeflop-update-sexpr
- Build a 4v-sexpr with the update function upon a posedge.
- Vl-nedgeflop-e-wires
- Vl-make-delay-assigns
- Vl-nedgeflop-posedge-clks
- Build the Verilog sensitivity list for a primitive n-edge flop.
- Vl-nedgeflop-data-mux
- Vl-nedgeflop-some-edge-sexpr
- Build a 4v-sexpr that captures when any clock has just had a posedge.
- Vl-modinsts-add-atts
- Vl-nedgeflop-or-edges
