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A transformation which "fills in" blank arguments.
Verilog permits the use of "blank" expressions as arguments to module and gate instances. See vl-port-p and vl-plainarg-p for some additional discussion.
This transformation "fills in" any blank arguments that are connected to non-blank ports with new, fresh wires. A related (but separate) transformation is drop-blankports which eliminates any blank ports and their corresponding arguments.
If a blank argument is given to a submodule's non-blank input port, it is the equivalent of passing in a Z value. If a blank argument is given to a submodule's non-blank output port, the value being emitted on that port is simply inaccessible in the superior module.
In either case, we simply replace the blank argument with a new, fresh,
otherwise undriven wire of the appropriate size. This approach works equally
well for inputs and outputs. We give these wires names such as
Unlike drop-blankports which can be applied at any time after argresolve, the blankargs transformation requires that expression sizes have been computed (see expression-sizing) since the new wires need to have the appropriate size. We also expect that the replicate-insts transform has been run to ensure that no instances have ranges.