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Transforms

Always-top

Transforms for synthesizing always blocks.

Subtopics

Edgesynth: Synthesize simple edge-triggered always blocks into primitives.
Stmtrewrite: Rewrite statements into simpler forms.
Cblock: Transform simple, purely combinational always and always_comb blocks into corresponding assign statements, replacing registers with wiring.
Vl-always-convert-regports: (vl-always-convert-regports x) maps vl-always-convert-regport across a list.
Vl-always-convert-regs: (vl-always-convert-regs x) maps vl-always-convert-reg across a list.
Stmttemps: Replace if conditions and right-hand sides into temporary wires.
Edgesplit: Split up edge-triggered always blocks that write to multiple registers.
Vl-always-check-reg: See if a register is simple enough to reasonably synthesize into a flop/latch.
Vl-convert-regs
Latchsynth: Main transform for synthesizing simple latch-like always blocks into instances of primitive latch modules.
Vl-always-check-regs
Vl-match-always-at-some-edges: Recognize and decompose edge-triggered statements.
Unelse: Convert if/else statements into blocks of independent if-statements.
Vl-always-convert-reg: Convert a register into a wire.
Vl-design-always-backend: Normal way to process always blocks after sizing.
Vl-stmt-guts: Coerce a statement into a statement list.
Vl-always-convert-regport: Convert a reg portdecl into a wire portdecl.
Vl-always-scary-regs: Determine which lvalues are assigned to in multiple always blocks.
Eliminitial: Throw away any initial statements and add non-fatal warnings to the affected modules.
Ifmerge: Merge nested if statements and blocks.
Vl-edge-control-p: Recognize @(posedge clk1 or negedge clk2 or ...) style event controls.
Elimalways: Add fatal warnings to any modules with always blocks, and throw away all always blocks.