Annotate
A first step in most transformation sequences. Applies several
basic, preliminary transforms to normalize the original design.
Subtopics
- Make-implicit-wires
- Add declarations for implicit wires.
- Resolve-indexing
- Resolve :vl-index operators that are applied to simple
bitvectors into :vl-bitselect operators.
- Origexprs
- Add VL_ORIG_EXPR annotations to some expressions.
- Argresolve
- Converts named argument lists into plain argument lists, and
annotates each plain argument with its direction.
- Portdecl-sign
- Fix up type (signedness) information between port and variable
declarations.
- Designwires
- Introduce VL_DESIGN_WIRE annotations that say which wires/regs
were in the original Verilog modules.
- Udp-elim
- Eliminate user-defined primitives (UDPs), replacing them with
equivalent modules.
- Vl-annotate-design
- Top level annotate transform.
