		Search-engine friendly clone of the ACL2 documentation.

Parser

Parse-blockitems

Functions for parsing Verilog and SystemVerilog block items.

The Verilog-2005 grammar for regs and variables is, after filtering out some duplication and indirection:

integer_declaration  ::= 'integer'  list_of_variable_identifiers ';'
real_declaration     ::= 'real'     list_of_variable_identifiers ';'
time_declaration     ::= 'time'     list_of_variable_identifiers ';'
realtime_declaration ::= 'realtime' list_of_variable_identifiers ';'
reg_declaration      ::= 'reg' [ 'signed' ] [ range ] list_of_variable_identifiers ';'

list_of_variable_identifiers ::= variable_type { ',' variable_type }

variable_type ::= identifier { range }
                | identifier '=' expression

For SystemVerilog-2012 this is quite a bit more complex. Quick rundown:

additional 'const', 'var', and lifetime specifiers
variables can be of many new built-in or user-defined types
initializers can have "new", etc., instead of just being expressions
ranges for each variable_type can now be lists of variable_dimensions
package import statements and typedefs are also considered data declarations, for whatever reason.

The new grammar looks like this:

data_declaration ::=
    ['const'] ['var'] [lifetime] data_type_or_implicit list_of_variable_decl_assignments ';'
  | ...

data_type_or_implicit ::= data_type
                        | implicit_data_type

implicit_data_type ::= [ signing ] { packed_dimension }

list_of_variable_decl_assignments ::= variable_decl_assignment { ',' variable_decl_assignment }

variable_decl_assignment ::=
     identifier { variable_dimension } [ '=' expression ]
   | identifier unsized_dimension { variable_dimension } [ '=' dynamic_array_new ]
   | identifier [ '=' class_new ]

dynamic_array_new ::= 'new' '[' expression ']' [ '(' expression ')' ]

class_new ::= [ class_scope ] 'new' [ '(' list_of_arguments ')' ]
            | 'new' expression


variable_dimension ::= unsized_dimension
                     | unpacked_dimension
                     | associative_dimension
                     | queue_dimension

unsized_dimension     ::= '[' ']'
packed_dimension      ::= '[' constant_range ']' | unsized_dimension
associative_dimension ::= '[' data_type ']' | '[' '*' ']'
queue_dimension       ::= '[' '$' [ ':' expression ] ']'

list_of_arguments ::= [expression] { ',' [expression] } { ',' '.' identifier '(' [expression] ')' }
                    | '.' identifier '(' [expression] ')' { ',' '.' identifier '(' [expression] ')' }

Subtopics

Vl-ranges->dimensions: (vl-ranges->dimensions x) maps vl-range->dimension across a list.
Vl-2005-parse-block-item-declaration-noatts: Match a whole block_item_declaration, except for any attributes, for Verilog-2005.
Vl-2012-parse-block-item-declaration-noatts: Match a whole block_item_declaration, except for any attributes, for SystemVerilog-2012.
Vl-parse-main-data-declaration: Parse the main variable declaration part of a data_declaration for SystemVerilog-2012.
Vl-parse-type-declaration: Match any kind of type_declaration for SystemVerilog-2012.
Vl-parse-fwd-typedef: Match a forward type_declaration for SystemVeriog-2012.
Vl-parse-0+-block-item-declarations: Match as many block_item_declarations as we can find.
Vl-parse-list-of-event-identifiers: Match list_of_event_identifiers for Verilog-2005.
Vl-parse-list-of-variable-identifiers: Match list_of_variable_identifiers for Verilog-2005.
Vl-parse-realtime-declaration: Match realtime_declaration for Verilog-2005.
Vl-parse-block-item-declaration-noatts: Match a whole block_item_declaration, except for any attributes.
Vl-parse-time-declaration: Match time_declaration for Verilog-2005.
Vl-parse-reg-declaration: Match reg_declaration for Verilog-2005.
Vl-parse-real-declaration: Match real_declaration for Verilog-2005.
Vl-parse-integer-declaration: Match integer_declaration for Verilog-2005.
Vl-build-vardecls
Vl-parse-event-declaration: Match event_declaration for Verilog-2005.
Vl-parse-block-item-declaration: Match a whole block_item_declaration, including initial attributes.
Vl-parse-1+-let-ports
Vl-parse-variable-type: Match variable_type for Verilog-2005.
Vl-parse-let-declaration
Vl-parse-0+-let-ports