Reflects special case where the block
doesn't create a scope, in case of nested
conditionals. See SystemVerilog-2012
27.5: a block within a conditional construct
that has only one element, and is not
surrounded by begin/end keywords, is not
treated as a separate scope.
See the documentation for vl-genbegin. A
vl-genblock may represent an explicit begin/end
construct, or might instead be something like the true or
false branch of an if/else generate construct,
etc.