Implemented-opcodes
Intel opcodes supported in x86isa.
We support decoding of all the x86 instructions in the one-, two-, and
three-byte opcode maps, including the AVX/AVX2/AVX512 extensions. However, a
fraction of those are actually implemented in this model --- when we say
implemented instructions, we mean instructions that have a semantic function
that models its effects on the machine's state.
For a listing of all such supported instructions, see one-byte-opcodes-map, two-byte-opcodes-map, 0f-38-three-byte-opcodes-map, and 0f-3a-three-byte-opcodes-map.
For a readable version of all the opcode maps, see constants like
*pre-one-byte-opcode-map* in the book inst-listing.lisp. These are
the constants to edit in order to add new instructions, etc. in the future.
The dispatch, modr/m and prefixes computation, and generation of
documentation is done automatically from these constants.
Subtopics
- Two-byte-opcodes-map
- List of implemented instructions whose opcode is two bytes long,
beginning with 0F; includes VEX/EVEX instructions too
- One-byte-opcodes-map
- List of implemented instructions whose opcode is one byte long
- 0f-38-three-byte-opcodes-map
- List of implemented instructions whose opcode is three bytes
long, beginning with 0F_38; includes VEX/EVEX instructions too
- 0f-3a-three-byte-opcodes-map
- List of implemented instructions whose opcode is three bytes
long, beginning with 0F_3A; includes VEX/EVEX instructions too
