Build the Verilog if-statement for a primitive n-edge flop.
(vl-nedgeflop-ifstmt q-expr clk-exprs data-exprs) → guts
Function:
(defun vl-nedgeflop-ifstmt (q-expr clk-exprs data-exprs) (declare (xargs :guard (and (vl-expr-p q-expr) (vl-exprlist-p clk-exprs) (vl-exprlist-p data-exprs)))) (declare (xargs :guard (and (consp clk-exprs) (same-lengthp clk-exprs data-exprs)))) (let ((__function__ 'vl-nedgeflop-ifstmt)) (declare (ignorable __function__)) (b* (((when (atom clk-exprs)) (impossible) (make-vl-nullstmt)) (assign1 (make-vl-assignstmt :type :vl-nonblocking :lvalue q-expr :expr (car data-exprs) :loc *vl-fakeloc*)) ((when (atom (cdr clk-exprs))) assign1)) (make-vl-ifstmt :condition (car clk-exprs) :truebranch assign1 :falsebranch (vl-nedgeflop-ifstmt q-expr (cdr clk-exprs) (cdr data-exprs))))))
Theorem:
(defthm vl-stmt-p-of-vl-nedgeflop-ifstmt (implies (and (force (vl-expr-p q-expr)) (force (vl-exprlist-p clk-exprs)) (force (vl-exprlist-p data-exprs)) (force (consp clk-exprs)) (force (same-lengthp clk-exprs data-exprs))) (b* ((guts (vl-nedgeflop-ifstmt q-expr clk-exprs data-exprs))) (vl-stmt-p guts))) :rule-classes :rewrite)