Creating-portdecls/vardecls
Utilities for the initial creation of port declarations and (if the
port declaration is complete) corresponding net declarations.
The creation of port declarations and net declarations is very
subtle. See also portdecl-sign and make-implicit-wires.
From Verilog-2005, page 174:
- If a port declaration includes a net or variable type, then the port is
considered completely declared and it is an error for the port to be declared
again in a variable or net data type declaration...
- If the port declaration does NOT include a net or variable type, then the
port can be declared again in a net or variable declaration. If the net or
variable is declared as a vector, the range specification between the two
declarations shall be identical.
So if the parser encounters a port declaration with a net or variable type,
the port is completely declared and we are going to generate both (1) a port
declaration and (2) the corresponding net declaration.
However, if we have no net type, then we'll instead only add the port
declaration, which we will mark with the attribute
VL_INCOMPLETE_DECLARATION. The corresponding net will either be found
later in the module, or will be added automatically with the make-implicit-wires transform. Signedness is handled last, by portdecl-sign.
Subtopics
- Vl-make-ports-and-maybe-nets
- Top level routine for creating proper port and variable declarations.
- Vl-parsed-port-identifier-p
- Temporary structure created during port parsing.
- Vl-build-portdecls
- Main loop for creating real vl-portdecls.
- Vl-build-netdecls-for-ports
- Main loop for creating the associated vl-vardecls.
- Vl-parsed-port-identifier-list-from-idtokenlist
- Convert idtokens into trivial vl-parsed-port-identifier-ps.
- Vl-parsed-port-identifier-list-p
- (vl-parsed-port-identifier-list-p x) recognizes lists where every element satisfies vl-parsed-port-identifier-p.
