Functions for parsing Verilog and SystemVerilog block items.
The Verilog-2005 grammar for regs and variables is, after filtering out some duplication and indirection:
integer_declaration ::= 'integer' list_of_variable_identifiers ';' real_declaration ::= 'real' list_of_variable_identifiers ';' time_declaration ::= 'time' list_of_variable_identifiers ';' realtime_declaration ::= 'realtime' list_of_variable_identifiers ';' reg_declaration ::= 'reg' [ 'signed' ] [ range ] list_of_variable_identifiers ';' list_of_variable_identifiers ::= variable_type { ',' variable_type } variable_type ::= identifier { range } | identifier '=' expression
For SystemVerilog-2012 this is quite a bit more complex. Quick rundown:
The new grammar looks like this:
data_declaration ::= ['const'] ['var'] [lifetime] data_type_or_implicit list_of_variable_decl_assignments ';' | ... data_type_or_implicit ::= data_type | implicit_data_type implicit_data_type ::= [ signing ] { packed_dimension } list_of_variable_decl_assignments ::= variable_decl_assignment { ',' variable_decl_assignment } variable_decl_assignment ::= identifier { variable_dimension } [ '=' expression ] | identifier unsized_dimension { variable_dimension } [ '=' dynamic_array_new ] | identifier [ '=' class_new ] dynamic_array_new ::= new [ expression ] [ ( expression ) ] class_new ::= [ class_scope ] new [ ( list_of_arguments ) ] | new expression variable_dimension ::= unsized_dimension | unpacked_dimension | associative_dimension | queue_dimension unsized_dimension ::= '[' ']' packed_dimension ::= '[' constant_range ']' | unsized_dimension associative_dimension ::= '[' data_type ']' | '[' '*' ']' queue_dimension ::= '[' '$' [ ':' expression ] ']' list_of_arguments ::= [expression] { ',' [expression] } { ',' '.' identifier '(' [expression] ')' } | '.' identifier '(' [expression] ')' { ',' '.' identifier '(' [expression] ')' }