Generate an N-bit register with K edges.
(vl-make-nedgeflop width nedges) → mods
Function:
(defun vl-make-nedgeflop (width nedges) (declare (xargs :guard (and (posp width) (posp nedges)))) (let ((__function__ 'vl-make-nedgeflop)) (declare (ignorable __function__)) (b* ((width (lposfix width)) (nedges (lposfix nedges)) ((when (eql width 1)) (list (vl-make-1-bit-n-edge-flop nedges))) (name (cat "VL_" (natstr width) "_BIT_" (natstr nedges) "_EDGE_FLOP")) ((mv q-expr q-port q-portdecl q-vardecl) (vl-occform-mkport "q" :vl-output width)) ((mv d-exprs d-ports d-portdecls d-vardecls) (vl-occform-mkports "d" 0 nedges :dir :vl-input :width width)) ((mv clk-exprs clk-ports clk-portdecls clk-vardecls) (vl-occform-mkports "clk" 0 nedges :dir :vl-input :width 1)) (primitive (vl-make-1-bit-n-edge-flop nedges)) (modinsts (vl-make-nedgeflop-insts primitive q-expr d-exprs clk-exprs width))) (list (make-vl-module :name name :origname name :ports (cons q-port (append d-ports clk-ports)) :portdecls (cons q-portdecl (append d-portdecls clk-portdecls)) :vardecls (cons q-vardecl (append d-vardecls clk-vardecls)) :modinsts modinsts :minloc *vl-fakeloc* :maxloc *vl-fakeloc*) primitive))))
Theorem:
(defthm vl-modulelist-p-of-vl-make-nedgeflop (b* ((mods (vl-make-nedgeflop width nedges))) (vl-modulelist-p mods)) :rule-classes :rewrite)
Theorem:
(defthm type-of-vl-make-nedgeflop (and (true-listp (vl-make-nedgeflop width nedges)) (consp (vl-make-nedgeflop width nedges))) :rule-classes :type-prescription)