Latchsynth
Main transform for synthesizing simple latch-like always blocks
into instances of primitive latch modules.
This is a sort of back-end transform that does the final conversion
of already-simplified always statements into latches. This is quite
similar to how the occform transform converts Verilog expressions into
explicit instances of generated modules, except that here we are converting
always statements into instances of latch modules.
Notes:
- We support only a very small set of always statements here; see latchcode. Typically you will want to run other statement-simplifying
transformations first to get them into this form; see always-top.
- We expect expressions to be sized so that we can tell which sizes of latch
modules to introduce.
- We expect modules to be free of initial statements, otherwise we could
produce invalid modules when we convert registers into nets.
- This is a best-effort style transform which will leave unsupported
always blocks alone. We usually follow up with elimalways to throw
out (with fatal warnings) modules whose always blocks were not
supported.
Subtopics
- Vl-module-latchsynth
- Synthesize simple latch-like always blocks in a module.
- Vl-modulelist-latchsynth-aux
- Vl-modulelist-latchsynth
- Synthesize latch-like always blocks in a module list, perhaps
adding some new, supporting modules.
- Vl-design-latchsynth
- Top-level latchsynth transform.
