Representation of a single Verilog bit (0, 1, X, or Z).
Verilog has four register-transfer level values,
This is an ordinary defenum.
Function:
(defun vl-bit-p (x) (declare (xargs :guard t)) (or (eq x ':vl-0val) (eq x ':vl-1val) (eq x ':vl-xval) (eq x ':vl-zval)))
Theorem: type-when-vl-bit-p
(defthm type-when-vl-bit-p (implies (vl-bit-p x) (if (symbolp x) (if (not (equal x 't)) (not (equal x 'nil)) 'nil) 'nil)) :rule-classes :compound-recognizer)