Vl-assignstmt
Representation of an assignment statement.
This is a product type, introduced by deftagsum in support of vl-stmt.
Fields
- type — vl-assign-type-p
- Kind of assignment statement, e.g., blocking, nonblocking, etc.
- lvalue — vl-expr
- Location being assigned to. Note that the Verilog-2005 standard
places various restrictions on lvalues, e.g., for a procedural
assignment the lvalue may contain only plain variables, and
bit-selects, part-selects, memory words, and nested
concatenations of these things. We do not enforce these
restrictions in vl-assignstmt-p, but only require that the
lvalue is an expression.
- expr — vl-expr
- The right-hand side expression that should be assigned to the
lvalue.
- ctrl — vl-maybe-delayoreventcontrol
- Control that affects when the assignment is done, if any. These
controls can be a delay like #(6) or an event control like
@(posedge clk). The rules for this are covered in Section
9.2 and appear to perhaps be different depending upon the type
of assignment. Further coverage seems to be available in
Section 9.7.7.
- atts — vl-atts
- Any attributes associated with this statement.
- loc — vl-location
- Where the statement was found in the source code.
Assignment statements are covered in Section 9.2. There are two
major types of assignment statements.
Procedural Assignments
Procedural assignment statements may only be used to assign to reg,
integer, time, realtime, and memory data types, and cannot be
used to assign to ordinary nets such as wires. There are two kinds of
procedural assignments:
foo = bar ; // "blocking" -- do the assignment now
foo <= bar ; // "nonblocking" -- schedule the assignment to occur
The difference between these two statements has to do with Verilog's timing
model and simulation semantics. In particular, a blocking assignment
"executes before the statements that follow it," whereas a non-blocking
assignment only "schedules" an assignment to occur and can be thought of as
executing in parallel with what follows it.
Continuous Procedural Assignments
Continuous procedural assignment statements may apparently be used to assign
to either nets or variables. There are two kinds:
assign foo = bar ; // only for variables
force foo = bar ; // for variables or nets
We represent all of these kinds of assignment statements uniformly as
vl-assignstmt-p objects.
SystemVerilog Extensions
SystemVerilog-2012 implements special additional assignment operators such
as a += b. Per Section 11.4 of SystemVerilog-2012, these operators are
semantically equivalent to blocking assignment statements except that in the
case of index expressions such as a[i] += b, the index i is only
evaluated once. VL's parser converts assignments such as a += b into
blocking assignments such as a = a + b. To note that this was a +=
style assignment, the parser adds a VL_FANCY_ASSIGNMENT_OPERATOR attribute
to the assignstmt.
SystemVerilog also adds increment and decrement operators, i.e., a++
and a--. These operators, per Section 11.4.2 of SystemVerilog-2012, also
"behave as blocking assignments." VL2014 does not really support these
operators but they may be supported in the newer vl.
Subtopics
- Make-vl-assignstmt
- Basic constructor macro for vl-assignstmt structures.
- Vl-assignstmt->ctrl
- Get the ctrl field from a vl-assignstmt.
- Vl-assignstmt->lvalue
- Get the lvalue field from a vl-assignstmt.
- Vl-assignstmt->expr
- Get the expr field from a vl-assignstmt.
- Vl-assignstmt->type
- Get the type field from a vl-assignstmt.
- Vl-assignstmt->loc
- Get the loc field from a vl-assignstmt.
- Vl-assignstmt->atts
- Get the atts field from a vl-assignstmt.
- Change-vl-assignstmt
- Modifying constructor for vl-assignstmt structures.
