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• Parse-ports

Verilog-2005-portdecls

Parsing for Verilog-2005 port declarations.

Here is the grammar we're implementing.

port_declaration ::= {attribute_instance} inout_declaration
                   | {attribute_instance} input_declaration
                   | {attribute_instance} output_declaration

inout_declaration ::= 'inout' [net_type] ['signed'] [range] list_of_port_identifiers

input_declaration ::= 'input' [net_type] ['signed'] [range] list_of_port_identifiers

output_declaration ::= 'output' [net_type] ['signed'] [range] list_of_port_identifiers
                     | 'output' 'reg' ['signed'] [range] list_of_variable_port_identifiers
                     | 'output' output_variable_type list_of_variable_port_identifiers

net_type ::= 'supply0' | 'supply1' | 'tri' | 'triand' | 'trior' | 'tri0' | 'tri1'
           | 'uwire' | 'wire' | 'wand' | 'wor'

list_of_port_identifiers ::= identifier { ',' identifier }

list_of_variable_port_identifiers ::=
   identifier ['=' expression] { ',' identifier [ '=' expression ] }

output_variable_type ::= 'integer' | 'time'

list_of_port_declarations ::= '(' port_declaration { ',' port_declaration } ')'
                            | '(' ')'

Subtopics

Vl-parse-basic-port-declaration-tail

Matches [net_type] ['signed'] [range] list_of_port_identifiers.

Vl-parse-port-declaration-noatts-2005

Verilog-2005 Only. Match inout_declaration | input_declaration | output_declaration.

Vl-parse-port-declaration-atts-2005

Verilog-2005 Only. Matches port_declaration in ansi-style port lists.

Vl-parse-1+-identifiers-separated-by-commas

Matches identifier { ',' identifier }

Vl-parse-port-declaration-noatts

Matches port_declaration for Verilog-2005 or SystemVerilog-2012, except for the initial attributes. Used for port declarations within modules.

Vl-parse-output-reg-port-tail

We've just matched 'output reg'. Now match ['signed'] [range] list_of_variable_port_identifiers.