Verilog-2005-ports
Parsing for Verilog-2005 ports.
In Verilog-2005, a port_expression is just a syntactic means
to restrict the expressions allowed in ports to identifiers, bit-selects,
part-selects, and concatenations. We just parse port_expressions into
plain expressions.
port_expression ::= port_reference
| '{' port_reference { ',' port_reference } '}'
port_reference ::= identifier [ '[' constant_range_expression ']' ]
constant_range_expression ::= constant_expression
| msb_constant_expression : lsb_constant_expression
Port expressions are put into lists with the following rules.
list_of_ports ::= '(' port { ',' port } ')'
port ::= [port_expression]
| '.' identifier '(' [port_expression] ')'
Note that the above rules allow null ports, e.g., module foo ( a, , b
). As described in 12.3.2, the port expression is optional to allow for
ports that do not connect to anything internal to the module.
If we were to interpret the grammar very literally, the list_of_ports
for module foo () would be a singleton list with a blank port. But in
light of the way module instances work, e.g., see special-note-about-blank-ports, it seems like the nicest way to handle this is
to instead allow an empty list of ports, and treat () as producing the
empty list of ports instead of a single blank port.
Subtopics
- Vl-parse-module-port-list-top-2005
- Verilog-2005 only. Top-level function for parsing port lists in both
ANSI and non-ANSI styles.
- Vl-parse-module-port-list-top-2012
- SystemVerilog-2012 only. Top-level function for parsing port lists
in both ANSI and non-ANSI styles.
- Vl-parse-port-reference
- Matches port_reference.
- Vl-parse-1+-ports-separated-by-commas
- Matches port { ',' port }, possibly producing blank ports!
- Vl-parse-1+-port-references-separated-by-commas
- Matches port_reference { ',' port_reference }
- Vl-parse-nonnull-port
- Matches port, except for the empty port.
- Vl-parse-port-expression
- Matches port_expression.
- Vl-parse-module-port-list-top
- Vl-port-starts-ansi-port-list-p
- Determine whether we're in an ANSI or non-ANSI port list.
