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Representation of
This is a product type, introduced by deftagsum in support of vl-stmt.
foreach( <array> [ <var1>, ..., <varN> ] ) statement
See SystemVerilog-2012 section 12.7.3. The
The variable list allows us to introduce name variables corresponding to certain dimensions of the array. It should not mention more variables than the dimensions of the array. Variable names may also be omitted to indicate that we don't want to iterate through that particular dimension of the array. We represent these with a vl-maybe-exprlist so that you can tell when a variable has been omitted.
We infer a vl-vardecl from each loop variable. These
will be
logic [3:0][7:0][15:0] arr;
foreach (arr [i,j,k]) begin
$display("Size of i is %d", $bits(i));
$display("Size of j is %d", $bits(j));
$display("Size of k is %d", $bits(k));
end
should report sizes such as 2, 3, and 4. But commercial tools
seem to report a size of 32 bits for all of these variables, so we
think that in practice these are interpreted as