|
|
|---|
|
|
|
|---|
Representation for the actual values given to parameters.
This is a tagged union type, introduced by deftagsum.
In Verilog-2005, the values for a parameterized module were always ordinary expressions, e.g., 3 and 5 below.
myalu #(.delay(3), .width(5)) alu1 (...);
However, in SystemVerilog-2012 there can also be type parameters. For instance, a valid instance might look like:
myalu #(.delay(3), .Bustype(logic [63:0])) myinst (...);
The
param_expression ::= mintypmax_expression | data_type | '$'
But note that