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An indication of an integer expression's signedness (signed or unsigned).
On the surface there is not much to this: a literal, wire, or some other kind of expression might be regarded as either signed or unsigned. These notes about the signedness of things occur in the representation of certain expressions like vl-constint and vl-weirdint literals. There is some special handling for the signedness of ports; see portdecl-sign, but signedness is most critically used in vl-expr-typedecide.
Note about the word ``type.'' The Verilog-2005 and SystemVerilog-2012 standards sometimes use the word ``type'' to refer to the signedness of things. Back in Verilog-2005 there were no fancy types like structs and unions and the ``type'' of an expression generally meant whether it was a real number, a signed integer, an unsigned integer, and maybe other vaguely specified things.
With SystemVerilog-2012 adding much richer variable datatypes (see vl-datatype), it gets very confusing to use the word ``type'' in place of signedness. However, this is still done occasionally. Most notably, it happens in SystemVerilog-2012 Section 11.8.1, which is adapted from Verilog-2005's Section 5.5.1. This section explains how to compute the ``type'' of an expression, but in this context ``type'' still means signedness and has little to do with any kind of fancy SystemVerilog vl-datatype-like types.
The signedness of wires and variables in VL is now generally part
of their vl-datatype. Historically the way to query a type for
its signedness was to use