Four-valued semantics for a wired and.
(4v-wand a b) returns:
We use this to model what happens when multiple signals are connected in a wired and arrangement.
The full truth table is shown below. It intentionally corresponds to the Verilog semantics for wired ors (Section 4.6.2 of the Verilog 2005 specification).
| F T X Z | -----+------------------+ F | F F F F | T | F T X T | X | F X X X | Z | F T X Z | -----+------------------+
Function:
(defun 4v-wand (a b) (declare (xargs :guard t)) (mbe :logic (4vcases a (t (4vcases b (z (4vt)) (& (4v-fix b)))) (f (4vf)) (z (4v-fix b)) (& (4vcases b (f (4vf)) (& (4vx))))) :exec (cond ((eq a (4vf)) (4vf)) ((eq b (4vf)) (4vf)) ((eq a (4vt)) (if (or (eq b (4vt)) (eq b (4vz))) (4vt) (4vx))) ((eq a (4vz)) (if (or (eq b (4vt)) (eq b (4vz))) b (4vx))) (t (4vx)))))
Theorem:
(defthm 4v-wand-truth-table (and (equal (4v-wand (4vf) (4vf)) (4vf)) (equal (4v-wand (4vf) (4vt)) (4vf)) (equal (4v-wand (4vf) (4vx)) (4vf)) (equal (4v-wand (4vf) (4vz)) (4vf)) (equal (4v-wand (4vt) (4vf)) (4vf)) (equal (4v-wand (4vt) (4vt)) (4vt)) (equal (4v-wand (4vt) (4vx)) (4vx)) (equal (4v-wand (4vt) (4vz)) (4vt)) (equal (4v-wand (4vx) (4vf)) (4vf)) (equal (4v-wand (4vx) (4vt)) (4vx)) (equal (4v-wand (4vx) (4vx)) (4vx)) (equal (4v-wand (4vx) (4vz)) (4vx)) (equal (4v-wand (4vz) (4vf)) (4vf)) (equal (4v-wand (4vz) (4vt)) (4vt)) (equal (4v-wand (4vz) (4vx)) (4vx)) (equal (4v-wand (4vz) (4vz)) (4vz))) :rule-classes nil)
Theorem:
(defthm 4v-equiv-implies-equal-4v-wand-2 (implies (4v-equiv b b-equiv) (equal (4v-wand a b) (4v-wand a b-equiv))) :rule-classes (:congruence))
Theorem:
(defthm 4v-equiv-implies-equal-4v-wand-1 (implies (4v-equiv a a-equiv) (equal (4v-wand a b) (4v-wand a-equiv b))) :rule-classes (:congruence))