A single member of a struct or union.
This is a product type introduced by defprod.
Currently our structure members are very limited. In the long
run we may want to support more of the SystemVerilog grammar. It allows a list
of variable declaration assignments, which can have fancy dimensions and
different kinds of
Notes for the future:
variable_decl_assignment ::= variable_identifier { variable_dimension } [ '=' expression ] | dynamic_array_variable_identifier unsized_dimension { variable_dimension } [ '=' dynamic_array_new ] | class_variable_identifier [ '=' class_new ]
These fancy _identifiers are all just identifiers. So really this is:
variable_decl_assignment ::= identifier { variable_dimension } [ '=' expression ] | identifier unsized_dimension { variable_dimension } [ '=' dynamic_array_new ] | identifier [ '=' class_new ]
The
function ... new (...) ...
And
The other places where
dynamic_array_new ::= new '[' expression ']' [ '(' expression ')' ] class_new ::= [ class_scope ] 'new' [ '(' list_of_arguments ')' ] | 'new' expression
Which in turn can occur in blocking assignments:
[some fancy lhs] = dynamic_array_new or [some other fancy lhs] = class_new or other things not involving new
(Which is interesting because we also have to support a lot of other new
kinds of assignments like
And they can also occur in variable decl assignments:
simple id [ = expression ] or some fancy lhs with some various dimensions [= dynamic_array_new] or some simple lhs [= class_new]
Which can occur in:
So maybe we don't so much need these to be expressions. Maybe we can get away with them as alternate kinds of assignments.