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Vwsim-output

Vwsim-output-request-format

How to format output requests from a VWSIM simulation.

Requesting Simulation Values

The user can request voltage, phase, and current values from a circuit simulation. The request types are:

NODEV - node (wire) voltage

NODEP - node (wire) phase

DEVV - voltage across device

DEVI - current through device

PHASE - phase difference across device

The request is a cons pair of the form (type . name). The type is paired with the name of a node or device. The name is expected to be of the form primitive-name/module-name/... (in SPICE, the names are separated by | instead of /), which is the flattened hierarchical name of the node or device. That is, the name consists of the primitive name, followed by the heirarchy of module (subcircuit) names that contain the primitive. For example, consider the following RC circuit with a module defined in SPICE syntax:

.SUBCKT SUB_DEF A C
  RR1 A B 1
  CC1 B C 1
.ENDS

VVS1 V1 GND pwl (0 0 1 1)
SUB0 A  GND SUB_DEF

After the circuit is flattened, the resistor has the name RR1/SUB0, the capacitor has name CC1/SUB0, and the voltage source has the name VVS1 (since it is a top-level device). If we wish to inspect the voltage across the resistor and the current through the capacitor after a simulation has been completed, we could construct the following association-list:

'((DEVV . RR1/SUB0)
  (DEVI . CC1/SUB0))

In SPICE, we would provide .print commands of the following form:

.print DEVV RR1|SUB0
.print DEVI CC1|SUB0

A complete table of acceptable requests is shown below. X indicates that the command can be used to get the value of that node or device.

	N	R	L	C	B	V	I	P	T
NODEV	X
NODEP	X
DEVV		X	X	X	X	X	X	X	X
DEVI		X	X	X	X	X	X	X	X
PHASE		X	X	X	X	X	X	X	X