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Always-top

Cblock

Transform simple, purely combinational always and always_comb blocks into corresponding assign statements, replacing registers with wiring.

Some basic criteria for treating an always block as combinational:

Expressions must be sized.
It must be a plain always block or an always_comb block.
Plain always blocks must be a sensitivity list. This sensitivity list may not mention any edge-triggered components (since if it does, this block isn't combinational). Moreover, the sensitivity list needs to be "correct": either it may be always @(*), or else it must correctly mention every net/reg that is used in an rvalue context, including if conditions and right-hand sides of assignments.
For simplicity, we don't try to handle sensitivity lists that include part- or bit-selects. That is, we support things like always @(a or b), but not always @(a[3] or b[17:0]).
We don't support assignments to variables in the sensitivity list (by which we really mean the set of right-hand side variables). This isn't necessarily wrong, but it is kind of weird because it means that evaluating the block will potentially trigger another evaluation of the block. This could perhaps lead to loops, and is generally confusing. For instance, consider:
```
always @@(a or c)
begin
   a = 1;
   a = c;
end
```
If c transitions to 0, then this block can start looping with itself, forever setting A to 1 and then back to 0. It might be possible to relax this restriction if it proves problematic, but this all gets very subtle.
The module may not have initial statements. We're going to want to convert each each lvalue reg into a wire, so if initial statements could be writing to these regs, then this conversion would produce a malformed module. Prohibiting initial statements is an easy way to avoid this.
All assignments must be delay-free, blocking assignments. Non-blocking assignments are appropriate for edge-triggered logic, not for combinational logic. Delays are not supported for simplicity.
The lvalue registers must never be assigned to by other always blocks. Having multiple always statements updating the same register is way too hard to think about. See vl-always-scary-regs.
Always blocks that update only a portion of a register (even if the specified range is the entire register) are not currently supported, since this leaves us without an easy way to convert the reg into a wire.
Each lvalue register must be assigned to in every branch. Otherwise we need to infer a latch, e.g., the following can't be turned into ordinary assign statements:
```
always @@(v1 or v2)
  if (v1)
     r = v2;
```
because r needs to keep its value when v1 is false. It wouldn't be correct to replace this block with assign r = v1 ? v2 : r, because that's a combinational loop.

Subtopics

Vl-stmt-cblock-p: Recognizer for very restricted statements that we (potentially) support in combinational always blocks; i.e., the valid guts for always @@(a or b or ...) guts.
Cblock-path-checking: How we check whether all of the variables assigned to in an always block are, indeed, assigned to in all paths. In other words: how we know that we don't need to infer a latch.
Cblock-expression-building: Convert a combinational always block into assignments.
Vl-stmt-cblock-lvalexprs: Collect expressions used in left-hand side positions.
Vl-stmt-cblock-rvalexprs: Collect expressions used in right-hand side positions (and if-statement conditions.)
Vl-classic-control->exprs: Simply get, e.g., (a b c ...) from @@(a or b or c or ...)
Vl-classic-control-p: Recognize Verilog-1995 style @(a or b or c or ...) sensitivity lists.
Vl-star-control-p: Recognize Verilog-2001 style @(*) sensitivity lists.