• Top
  • Documentation
  • Books
  • Boolean-reasoning
  • Projects
  • Debugging
  • Std
  • Community
  • Proof-automation
  • ACL2
  • Macro-libraries
  • Interfacing-tools
  • Hardware-verification
    • Gl
    • Esim
    • Vl2014
      • Warnings
      • Primitives
      • Use-set
      • Syntax
      • Getting-started
      • Utilities
      • Loader
        • Preprocessor
        • Vl-loadconfig
        • Lexer
        • Vl-loadstate
        • Parser
          • Parse-expressions
          • Parse-udps
          • Vl-genelements
          • Parse-paramdecls
          • Parse-blockitems
          • Parse-utils
          • Parse-insts
          • Parse-datatype
          • Parse-functions
          • Parse-datatypes
          • Parse-strengths
          • Vl-parse-genvar-declaration
          • Vl-parse
          • Parse-ports
            • Parse-port-types
            • Sv-ansi-portdecls
              • Vl-parsed-ansi-port-p
                • Vl-parsed-ansi-port
                • Make-vl-parsed-ansi-port
                • Change-vl-parsed-ansi-port
                • Make-honsed-vl-parsed-ansi-port
                • Honsed-vl-parsed-ansi-port
                • Vl-parsed-ansi-port->id
                • Vl-parsed-ansi-port->head
                • Vl-parsed-ansi-port->dir
                • Vl-parsed-ansi-port->atts
              • Vl-parse-ansi-port-header
              • Vl-parse-ansi-port-declaration
              • Vl-parse-1+-ansi-port-declarations
              • Vl-parsed-interface-head
              • Vl-parse-optional-port-direction
              • Vl-parsed-ansi-portlist-p
              • Vl-parsed-ansi-head
              • *vl-directions-kwds*
              • *vl-directions-kwd-alist*
            • Creating-portdecls/vardecls
            • Sv-non-ansi-portdecls
            • Verilog-2005-ports
            • Sv-ansi-port-interpretation
            • Verilog-2005-portdecls
          • Seq
          • Parse-packages
        • Vl-load-merge-descriptions
        • Scope-of-defines
        • Vl-load-file
        • Vl-flush-out-descriptions
        • Vl-description
        • Vl-loadresult
        • Vl-read-file
        • Vl-find-basename/extension
        • Vl-find-file
        • Vl-read-files
        • Extended-characters
        • Vl-load
        • Vl-load-main
        • Vl-load-description
        • Vl-descriptions-left-to-load
        • Inject-warnings
        • Vl-load-descriptions
        • Vl-load-files
        • Vl-load-summary
        • Vl-collect-modules-from-descriptions
        • Vl-descriptionlist
      • Transforms
      • Lint
      • Mlib
      • Server
      • Kit
      • Printer
      • Esim-vl
      • Well-formedness
    • Sv
    • Fgl
    • Vwsim
    • Vl
    • X86isa
    • Svl
    • Rtl
  • Software-verification
  • Math
  • Testing-utilities

• Vl-parsed-ansi-port-p

Honsed-vl-parsed-ansi-port

Raw constructor for honsed vl-parsed-ansi-port-p structures.

Syntax:

(honsed-vl-parsed-ansi-port dir head id atts)

This is identical to vl-parsed-ansi-port, except that we hons the structure we are creating.

Definition

This is an ordinary honsing constructor introduced by defaggregate.

Function: honsed-vl-parsed-ansi-port

(defun honsed-vl-parsed-ansi-port (dir head id atts)
 (declare (xargs :guard (and (vl-maybe-direction-p dir)
                             (vl-parsed-ansi-head-p head)
                             (vl-parsed-port-identifier-p id)
                             (vl-atts-p atts))))
 (mbe
  :logic (vl-parsed-ansi-port dir head id atts)
  :exec
  (hons
       :vl-parsed-ansi-port (hons (hons dir head) (hons id atts)))))