Sv-ansi-port-interpretation
SystemVerilog-2012 rules for determining port kind/type/direction for
ANSI ports (Section 23.2.2.3).
SystemVerilog has some tricky rules for how ANSI port lists are
interpreted. For instance, in a module like:
module foo (output o,
input logic [3:0] a, b, c) ;
...
endmodule
The input logic [3:0] part gets used for a, b, and c.
Our actual parsing routines (see sv-ansi-portdecls) don't try to follow
these rules. Instead, they give us a list of "raw" vl-parsed-ansi-port-p structures, which we then need to convert into actual
ports, port declarations, and variable declarations.
Subtopics
- Vl-process-subsequent-ansi-port
- Vl-process-first-ansi-port
- Vl-process-subsequent-ansi-ports
- Vl-nettype-for-parsed-ansi-port
- Determine the net type to use for a port.
- Vl-parse-module-port-list-top-2012
- SystemVerilog-2012 only. Top-level function for parsing port lists
in both ANSI and non-ANSI styles.
- Vl-process-ansi-ports
- Top level function for turning parsed ansi port declarations into proper VL structures.
- Vl-port-starts-ansi-port-list-p
- Determine whether we're in an ANSI or non-ANSI port list.
- Vl-parse-module-port-list-top
- Vl-genelementlist->portdecls
