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• Primitives

*vl-1-bit-buf*

Primitive buffer module.

The Verilog definition of this module is:

module VL_1_BIT_BUF (out, in) ;
  output out;
  input in;
  assign out = |in;
endmodule

VL takes this as a primitive. We use this in place of buf gates, but probably not for much else since ordinary assignments are handled with *vl-1-bit-assign*, instead.

The corresponding esim primitive is ACL2::*esim-buf*.

We once tried to implement this primitive using out = ~ (~in), but found that NCVerilog (incorrectly) canceled the double negation and could hence produce Z bits on the output. The or-based definition above does not appear to have this problem.

Definition: *vl-1-bit-buf*

(defconst *vl-1-bit-buf*
 (b*
  ((name "VL_1_BIT_BUF")
   (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
   ((mv out-expr
        out-port out-portdecl out-vardecl)
    (vl-primitive-mkport "out" :vl-output))
   ((mv in-expr in-port in-portdecl in-vardecl)
    (vl-primitive-mkport "in" :vl-input))
   (assign
     (make-vl-assign :lvalue out-expr
                     :expr (make-vl-nonatom :op :vl-unary-bitor
                                            :args (list in-expr)
                                            :finalwidth 1
                                            :finaltype :vl-unsigned)
                     :loc *vl-fakeloc*)))
  (hons-copy
       (make-vl-module :name name
                       :origname name
                       :ports (list out-port in-port)
                       :portdecls (list out-portdecl in-portdecl)
                       :vardecls (list out-vardecl in-vardecl)
                       :assigns (list assign)
                       :minloc *vl-fakeloc*
                       :maxloc *vl-fakeloc*
                       :atts atts
                       :esim acl2::*esim-buf*))))