Primitive cmos transistor.
The Verilog meaning of this module is:
module VL_1_BIT_CMOS (out, data, nctrl, pctrl); output out ; input data ; input nctrl ; input pctrl ; cmos gate (out, data, nctrl, pctrl) ; endmodule
VL takes this as a primitive. The gate-elim transform converts
certain
ESIM has very little support for transistors, but this may be a useful target for other back-end tools. The corresponding esim primitive is ACL2::*esim-cmos*.
Definition:
(defconst *vl-1-bit-cmos* (b* ((name "VL_1_BIT_CMOS") (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF"))) ((mv out-expr out-port out-portdecl out-vardecl) (vl-primitive-mkport "out" :vl-output)) ((mv data-expr data-port data-portdecl data-vardecl) (vl-primitive-mkport "data" :vl-input)) ((mv nctrl-expr nctrl-port nctrl-portdecl nctrl-vardecl) (vl-primitive-mkport "nctrl" :vl-input)) ((mv pctrl-expr pctrl-port pctrl-portdecl pctrl-vardecl) (vl-primitive-mkport "pctrl" :vl-input)) (gate (make-vl-gateinst :type :vl-cmos :name "gate" :args (list (make-vl-plainarg :expr out-expr :dir :vl-output) (make-vl-plainarg :expr data-expr :dir :vl-input) (make-vl-plainarg :expr nctrl-expr :dir :vl-input) (make-vl-plainarg :expr pctrl-expr :dir :vl-input)) :loc *vl-fakeloc*))) (hons-copy (make-vl-module :name name :origname name :ports (list out-port data-port nctrl-port pctrl-port) :portdecls (list out-portdecl data-portdecl nctrl-portdecl pctrl-portdecl) :vardecls (list out-vardecl data-vardecl nctrl-vardecl pctrl-vardecl) :gateinsts (list gate) :minloc *vl-fakeloc* :maxloc *vl-fakeloc* :atts atts :esim acl2::*esim-cmos*))))