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• Primitives

*vl-1-bit-nmos*

Primitive nmos transistor.

The Verilog meaning of this module is:

module VL_1_BIT_NMOS (out, data, ctrl);
  output out ;
  input data ;
  input ctrl ;
  nmos gate (out, data, ctrl) ;
endmodule

VL takes this as a primitive. The gate-elim transform converts certain nmos gates into instances of this module.

ESIM has very little support for transistors, but this may be a useful target for other back-end tools. The corresponding esim primitive is ACL2::*esim-nmos*.

Definition: *vl-1-bit-nmos*

(defconst *vl-1-bit-nmos*
 (b*
  ((name "VL_1_BIT_NMOS")
   (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
   ((mv out-expr
        out-port out-portdecl out-vardecl)
    (vl-primitive-mkport "out" :vl-output))
   ((mv data-expr
        data-port data-portdecl data-vardecl)
    (vl-primitive-mkport "data" :vl-input))
   ((mv ctrl-expr
        ctrl-port ctrl-portdecl ctrl-vardecl)
    (vl-primitive-mkport "ctrl" :vl-input))
   (gate
    (make-vl-gateinst :type :vl-nmos
                      :name "gate"
                      :args (list (make-vl-plainarg :expr out-expr
                                                    :dir :vl-output)
                                  (make-vl-plainarg :expr data-expr
                                                    :dir :vl-input)
                                  (make-vl-plainarg :expr ctrl-expr
                                                    :dir :vl-input))
                      :loc *vl-fakeloc*)))
  (hons-copy
       (make-vl-module
            :name name
            :origname name
            :ports (list out-port data-port ctrl-port)
            :portdecls (list out-portdecl
                             data-portdecl ctrl-portdecl)
            :vardecls (list out-vardecl data-vardecl ctrl-vardecl)
            :gateinsts (list gate)
            :minloc *vl-fakeloc*
            :maxloc *vl-fakeloc*
            :atts atts
            :esim acl2::*esim-nmos*))))