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• Primitives

*vl-1-bit-zmux*

Primitive tri-state buffer module.

The Verilog meaning of this module is:

module VL_1_BIT_ZMUX (out, sel, a);
  output out;
  input sel;
  input a;
  assign out = sel ? a : 1'bZ;
endmodule

VL takes this as a primitive. It is used in vl-mux-occform as the basis for conditional expressions with Z branches that are typically used to implement muxes.

Verilog truth table:

 sel    a    |   out         sel    a        out
-------------+---------     -------------+-----------
  0     0    |    z           x     0    |    x
  0     1    |    z           x     1    |    x
  0     x    |    z           x     x    |    x
  0     z    |    z           x     z    |    x
  1     0    |    0           z     0    |    x
  1     1    |    1           z     1    |    x
  1     x    |    x           z     x    |    x
  1     z    |    z           z     z    |    x

The corresponding esim primitive is ACL2::*esim-tri*, which drives its output to (tristate sel a); see ACL2::4v-tristate. This matches the Verilog truth table exactly.

Definition: *vl-1-bit-zmux*

(defconst *vl-1-bit-zmux*
 (b*
  ((name "VL_1_BIT_ZMUX")
   (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
   ((mv out-expr
        out-port out-portdecl out-vardecl)
    (vl-primitive-mkport "out" :vl-output))
   ((mv sel-expr
        sel-port sel-portdecl sel-vardecl)
    (vl-primitive-mkport "sel" :vl-input))
   ((mv a-expr a-port a-portdecl a-vardecl)
    (vl-primitive-mkport "a" :vl-input))
   (assign
    (make-vl-assign
        :lvalue out-expr
        :expr
        (make-vl-nonatom :op :vl-qmark
                         :args (list sel-expr a-expr |*sized-1'bz*|)
                         :finalwidth 1
                         :finaltype :vl-unsigned)
        :loc *vl-fakeloc*)))
  (hons-copy
       (make-vl-module
            :name name
            :ports (list out-port sel-port a-port)
            :portdecls (list out-portdecl sel-portdecl a-portdecl)
            :vardecls (list out-vardecl sel-vardecl a-vardecl)
            :assigns (list assign)
            :minloc *vl-fakeloc*
            :maxloc *vl-fakeloc*
            :atts atts
            :origname name
            :esim acl2::*esim-tri*))))