CS395T: Technology Driven Computer Architecture

Course: Technology Driven Computer Architecture
CS395T
Unique Number: #50259
Instructor: Stephen W. Keckler
Taylor Hall 5.110
phone: 471-9763
skeckler@cs.utexas.edu
Office Hours: Monday 1-3, Tuesday 10-12, or by appointment
Class Meetings: MW 10-11:15, Taylor 3.144
Class Information: http://www.cs.utexas.edu/users/skeckler/CS395T
cs395t-tdca@cs.utexas.edu
Objectives: Students will develop an understanding of the relationship between technology and computer system design, as well as practice critical research and communication skills.
Prerequisites: Prospective students should have graduate standing and proficiency in computer architecture (CS352 or equivalent). Enrollment may be limited to 20 students.
Grading: 20%: Critiques of papers
20%: Class discussion participation
30%: Discussion leading
30%: Project

Course Overview:

Since the invention of the transistor in 1947, advances in silicon processing technology has provided not just incremental, but quantum leaps in computer functionality and performance. We are fast approaching the capability to fabricate billion transistor chips that can run at gigahertz clock rates. However, with this advancing technology comes new challenges for the computer designer. Wires and communication, rather than transistors and computation, have now become the most critical resource. While technological constraints will limit the scalability of modern-day implementations, the changing balance between communication and computation will provide opportunities for innovative architectures to match the demands of emerging applications with the capabilities of the underlying technology.

This course will examine computer architectures for billion transistor chips from the perspective of technological capabilities and constraints. Readings will focus both on momentous technological breakthroughs and their implications, including high density solid-state memory, interconnection networks, and notable milestones of integration measured in transistors per chip. The topics of discussion will include VLSI scaling, integrated DRAM and processors, on and off-chip communication bandwidth, power consumption, tradeoffs between hardware and software, and novel techniques for using billions of transistors on a single chip.

The format of the class is lecture/discussion with a project during the second half of the course. The quality of this class and the benefit you gain from it is determined primarily by you and your classmates, so it is important that everyone read the papers and come prepared to participate in discussions. The assignments for this class will include the following:

Paper Critiques:
The paper critiques are designed to help you hone your skills of reading, analyzing, and synthesizing documents pertaining to the work of other researchers. For each class meeting you will turn in a brief (1/4 to 1/2 typewritten page) critique of that meeting's assigned paper(s). The brevity of the critique should force you to focus your attention on the most important aspects of the paper. Your critique is not a book report and should answer the following questions:

  • What are the 3 most important points of the paper?
  • What is one problem or weakness of the paper?
  • If the paper's topic is primarily architecture, what is the future of the architecture as technology improves?
  • If the paper's topic is primarily technology, what is it's most significant influence on computer architecture or systems?

If more than one paper is assigned, your critique should provide some comparison of the papers.

Collaboration and discussion outside of class is strongly encouraged, but each student will turn in her/his own critique. Grading will be based on a satisfactory(S)/not satisfactory(NS) scale, and not satisfactory critiques receive no credit. Critiques are due at the beginning of the class period, and no late critiques will be accepted.

You may skip up to 6 critiques during the term without penalty. A not satisfactory critique is equivalent to a skipped critique. The critiques should reflect insight that you have gained from the paper, so don't bother turning in the critique if you have not read the paper.

Discussion Facilitation:
Class meetings will be organized by groups of 3 or 4 students, who will do additional research beyond the assigned paper, develop a discussion plan, and lead the class discussion. Each student will help lead a class discussion approximately 4 times during the semester. Students will submit their class preferences to the instructor who will assign them to groups. Students who do not submit preferences will be assigned to class meetings by the instructor. Changes will be permitted at the instructor's discretion.

In researching for your discussion, a facilitation group should read the assigned paper thoroughly and find 3 papers of related or relevant work that are not already on the primary reading list (they may however be on the supplementary reading list). If you come across a cool paper that you think is extremely relevant, bring a copy to the instructor and it may be added to the supplemental reading list or be substituted into the assigned reading list.

At the beginning of the class period, the facilitation group will turn in the 3 related work papers and a discussion plan. The discussion plan is an outline that describes how you plan on spending the 75 minutes of class time. For example, if the assigned paper was entitled, "Widgets++: Taking Widget Technology to the Next Century", a discussion plan might include:

  • 15 minutes - present the main ideas of the paper including:
    • The main technology contributions required for advance widget design
    • The development of widgets in past or existing technologies
    • Why widgets are important for the future
  • 20 minutes - present and discuss the related/relevant work
  • 20 minutes - break up into small groups to talk about alternatives to widgets
  • 20 minutes - rejoin into main group and have small groups present their ideas
  • List of questions for the class to answer/discuss

Each facilitation group is free to choose how to spend the 75 minutes in class productively and may use a variety of techniques for presentation/discussion including: tag team presentation by facilitation group, small group discussions, mini-projects, etc. The expectation is that the classes will be lively, fun, and technically interesting.

After leading the discussion, each member of the facilitation group will write a brief self-evaluation of the group's performance. These self evaluations will be due to the instructor on the same day of the presentation and will include the following:

  • What went well in the presentation/discussion.
  • What parts of the presentation/discussion could be improved upon.
  • Grade for self (A, B, or C).
  • Grade for group (A, B, or C).

Part of the exercise of finding background material is learning to use the on-campus library and information resources. I highly recommend the INSPEC database (accessible through the on-line library web page: http://www.lib.utexas.edu) as a starting point. The introductory seminar "Electronic Sources for Engineering Information" is likely to be valuable and will be conducted by the library staff at the following times:

  • September 4, 2-3pm, ECJ 1.306
  • September 10, 3-4pm, ECJ 1.306

To summarize, the facilitation group will submit the following to the instructor:

  • Copies of the 3 related work papers
  • A discussion plan (one per facilitation group)
  • A self evaluation (one per group member)

Project:
The project assignment will be handed out on September 30. Projects will be performed in groups and it will require the you to perform technology projections and assessments, design and evaluate a system architecture, present your work to the class, and hand in a design document.

Handouts (postscript format):

Computation Engines:

DateDiscussion TopicDiscussion Leader(s)
Aug. 26 Administrative details, Course overview Keckler
Development of the Microprocessor
Aug. 31 "The History of the 4004", Federico Faggin, Marcian E. Hoff, Stanley Mazor, and Masatoshi Shima, IEEE Micro, vol. 16:6, December, 1996, pp. 10-20.

4004 Instruction Set (8.7MB)

Related Reading:
  • "Lithography and the Future of Moore's Law", Gordon E. Moore, Proceedings of the SPIE 1995, vol. 2440, pp. 2-17.
  • "A Participants Perspective", R. Gary Daniels, IEEE Micro, December 1996, vol. 16:6, pp. 21-31.
Keckler
Sep. 2 "MicroVAX 78032 Chip, a 32-Bit Microprocessor", Dan Dobberpuhl, Robert Supnik, and Richard Witek, Proceedings of the IEEE International Conference on Computer Design, October 1986, pp. 414-419.

Related Reading:
  • "Microarchitecture Choices (Implementation of the VAX)", Yale Patt, 22nd Annual International Workshop on Microprogramming and Microarchitecture, August 1989, pp. 213-216.
  • "VAX-11/780 - A Virtual Address Extension to the DEC PDP-11 Family", W.D. Strecker, National Computer Conference, 1978, pp. 967-979.
  • "Architecture Management for Ensuring Sortware Compatibility in the VAX Family of Computers", Dileep Bhandarkar, IEEE Computer, Feb. 1982, pp. 87-93.
  • "Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization", Dileep Bhandarkar and Douglas Clark, ASPLOS 1991, pp. 310-319.
Srinivasan, Shingal, Venkatachalam
Sep. 7 Labor day - no class
Sep. 9 "Introducing the Intel i860 64-Bit Microprocessor", Les Kohn and Neal Margulis, IEEE Micro, August 1989, pp. 15-30.

Related Reading:
  • "Performance and the i860 Microprocessor", Mark Atkins, IEEE Micro, October 1991, pp. 24-27, 72-78.
  • "Reduced Instruction Set Computers", David A. Patterson, Communications of the ACM, vol. 28:1, January 1985, pp. 8-21.
  • "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", R. M. Tomasulo, IBM Journal, January 1967, pp. 25-33.
Ferris, Husain
Sep. 14 "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor", Daniel Leibholz and Rahul Razdan, Proceedings of IEEE Compcon 97, February 1997, pp. 28-36.

"UltraSPARC-IIi: Expanding the Boundaries of a System on a Chip", Kevin B. Normoyle, Michael A. Csoppenszky, Allan Tzeng, Timothy P. Johnson, Christopher D. Furman, and Jamshid Mostoufi, IEEE Micro, March/April 1998, pp. 14-24.

Related Reading: 		Kothari, Sawada
The Future of Wires
Sep. 16 "Silicon Trends and Limits for Advanced Microprocessors", Mark Bohr, Communications of the ACM, March 1998, vol. 41:3, pp. 80-87.

Related Reading:
  • "Trends in CMOS Process Integration", Richard A. Chapman, Electrochemical Society Proceedings, Volume 97-3, pp. 413-427.
  • "Scaling Optoelectronic-VLSI Circuits into the 21st Century: A Technology Roadmap", Ashok V. Krishnamoorthy and David A. B. Miller, IEEE Journal of Selected Topics in Quantum Electronics, Vol. 2:1, April 1996, pp. 55-76.
  • "The National Technology Roadmap of Semiconductors", http://www.sematech.org/public/roadmap/index.htm
Bhargava, Srinivasan
Sep. 21 "Interconnect Fabrication Processes and the Development of Low-Cost Wiring for CMOS Products", T.J. Licata, E.G. Colgan, J.M.E. Harper, and S.E. Luce, IBM Journal of Research and Development, July 1995, vol. 39:4, pp. 419-435.

Related Reading:
  • "Why Wire Delays Will No Longer Scale for VLSI Chips", Neil Wilhelm, Sun Microsystems Laboratories TR-95-44, August, 1995.
  • "Designing for a Gigahertz", H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel A. Silberman, Jeffrey L. Burns, Stephen D. Posluszny, and Osamu Takahashi, IEEE Micro, May/June 1998, pp. 66-74.
  • "A 480MHz RISC Microprocessor in a 0.12um Leff CMOS Technology with Copper Interconnects", N. Rohrer, et. al. Proceedings of the 1998 IEEE International Solid-State Circuits Conference, pp. 240-241.
Keckler
Directions for Microprocessors
Sep. 23 "A VLIW Architecture for a Trace Scheduling Compiler", Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, and Paul K. Rodman, IEEE Transactions on Computers, August 1988, vol. 37:8, pp. 967-979.

Related Reading:
  • "Dynamic Scheduling Techniques for VLIW Processors", B. Ramakrishna Rau, Technical Report, HPLabs HPL-93-52, Jun. 1993.
  • "Dynamic Rescheduling: A Technique for Object Code Compatibility in VLIW Architectures", Thomas M. Conte and Sumedh W. Sathaye, Proceedings of the 28th Annual International Symposium on Microarchitecture (MICRO-28), 1995, pp. 208-218.
Ferris, Sawada
Sep. 28 "Complexity Effective Superscalar Processors", Subbarao Palacharla, Norman P. Jouppi, and J.E. Smith, Proceedings of the International Symposium on Computer Architecture, May 1997, pp. 206-218.

Related Reading:
  • "Quantifying the Complexity of Superscalar Processors", Subbarao Palacharla, Norman P. Jouppi, and J.E. Smith, University of Wisconsin Technical Report, CS-TR-96-1328, http://www.cs.wisc.edu/trs.html.
  • "The Microarchitecture of Superscalar Processors", James E. Smith and Gurindar E. Sohi, Proceedings of the IEEE, vol. 83:12, December, 1995, pp. 1609-1624.
  • "Beyond Superscalar RISC, What Next? An Almost Unbiased View", David A. Luick, IEEE International Solid State Circuits Conference, Februay 1998, pp. 86-87.
Srinivasan, Shinghal
Sep. 30 "Evaluation of Design Alternatives for a Multiprocessor Microprocessor", Basem A. Nayfeh, Lance Hammond, and Kunle Olukotun, Proceedings of the International Symposium on Computer Architecture, May 1996, pp. 67-77.

Project assignment distributed

Related Reading:
  • "Design and Implmentation of a Fast Crossbar Scheduler", Pankaj Gupta and Nick McKeown, Hot Interconnects VI, Stanford University, August 1998.
Kothari, Husain
Oct. 5 "Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor", Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, and Whay S. Lee, Proceedings of the International Symposium on Computer Architecture, June 1998, pp. 306-317.

Related Reading:
  • "Simultaneous Multithreading: Maximizing On-Chip Parallelism", Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy, Proceedings of the 22nd International Symposium On Computer Architecture, May 1995, pp. 392-403.
  • "The Tera Computer System", Robert Alverson, David Callahan, Daniel Cummings, Brian Koblenz, Allan Porterfield, and Burton Smith, Proceedings of the International Conference on Supercomputing, June 1990, pp. 1-6.
  • "Multiscalar Processors", Gurindar S. Sohi, Scott E. Breach, and T.N. Vijaykumar, Proceedings of the 22nd International Symposium On Computer Architecture, May 1995, pp. 414-425.
Keckler

Data Storage:

Primary Storage - RAM
Oct. 7 "One-Level Storage System", T. Kilburn, D.B.G. Edwards, M.J. Lanigan, and F.H. Sumner, IRE Transactions, April 1962, pp. 223-235.

Related Reading:
  • "Virtual Memory Management in the VAX/VMS Operating System", Henry M. Levy and Peter H. Lipman, IEEE Computer, vol. 15:3, March 1982, pp. 35-41.
  • "Efficient Software-Based Fault Isolation", Robert Wahbe, Steven Lucco, Thomas E. Anderson, and Susan L. Graham, 14th ACM Symposium on Operating Systems Principles, December 1993, pp. 203-216.
  • "Hardware Support for Fast Capability-based Addressing", Nicholas P. Carter, Stephen W. Keckler, and William J. Dally, Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI), October 1994, pp. 319-327.
Husain, Shinghal
Oct. 12 "Trends in Semiconductor Memories", Yasunao Katayama, IEEE Micro, November/December 1997, pp. 10-17.

"Direct Rambus Technology: The New Main Memory Standard", Richard Crisp, IEEE Micro, November/December 1997, pp. 18-28.

Related Reading:
  • "Limited Bandwidth to Affect Processor Design", Doug Burger, James R. Goodman, and Alain Kagi, IEEE Micro, vol. 17:6, November/December 1997, pp. 55-62.
  • "Direct Rambus Technology Disclosure", Rambus Inc. http://www.rambus.com, October 1997.
  • "SLDRAM Architecture and Functional Overview", Peter Gillingham, MOSAID Technologies Inc.
Bhargava, Kothari
Oct. 14 "A Case for Intelligent RAM", David Patterson, Tom Anderson, Neal Cardwell, Richard Fromm, Kimberly Keaton, Christoforos Kozyrakis, Randi Thomas, and Katherine Yelick, IEEE Micro, March/April 1997, pp. 34-44.

Related Reading:
  • "Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures", David Patterson, Krste Asanovic, Aaron Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos Kozyrakis, David Martin, Stylianos Perissakis, Noah Treuhaft, and Katherine Yelick, Proceedings of the International Conference on Computer Design, October 1997, pp. 2-7.
  • "A Multimedia 32b RISC Microprocessor with 16Mb DRAM", Toru Shimizu, et. al. Proceedings of the 1996 IEEE International Solid-State Circuits Conference (ISSCC), pp. 216-217.
Sawada
Oct. 19 "Active Pages: A Computation Model for Intelligent Memory", Mark Oskin, Frederic T. Chong, and Timothy Sherwood, Proceedings of the International Symposium on Computer Architecture, July 1998, pp. 192-203.

Related Reading:
  • "Low-Power Design of Page-Based Intelligent Memory", Mark Oskin, Frederic T. Chong, Aamir Farooqui, Timothy Sherwood, and Justin Hensley, Proceedings of the 1998 Power Driven Microarchitecture Workshop, pp. 55-60.
Bhargava
Oct. 21 "eNVy: A Non-Volatile, Main Memory Storage System", Michael Wu and Willy Zwaenepoel, Proceedings of the the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1994, pp. 86-97.

Related Reading:
  • "Non-Volatile Memory for Fast, Reliable File Systems", Mary Baker, Satoshi Asami, Etienne Deprit, John Ousterhout, and Margo Seltzer, Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V), October 1992, pp. 10-22.
  • "Beating the I/O Bottleneck: a Case for Log-Structured File Systems", John Ousterhout and Fred Douglis, Operating Systems Review, vol.23:1, January 1989, pp. 11-28.
Ferris
Secondary Storage - Disks
Oct. 26 "A Quarter Century of Disk File Innovation", J.M Harker, D.W. Brede, R.E. Pattison, G.R. Santana, and L.G. Taft, IBM Journal of Research and Development, September 1981, vol. 25:5, pp. 677-689.

Related Reading: 		Keckler
Oct. 28 "A Case for Redundant Arrays of Inexpensive Disks (RAID)", David A. Patterson, Garth Gibson, and Randy H. Katz, SIGMOD International Conference on Management of Data, SIGMOD Record, vol. 17:3, pp. 109-116.

Related Reading:
  • "RAID-II: Design and Implementation of a Large Scale Disk Array Controller", R.H. Katz, P.M. Chen, A.L. Drapeau, E.K. Lee, K. Lutz, E.L. Miller, S. Seshan, and D.A. Patterson, UC-Berkeley Tech Report, CSD-92-705.
  • "How Reliable is RAID", Martin Shultz, Garth Gibson, Randy Katz, and David Patterson, IEEE COMPCON Spring 1989, San Francisco, CA, February 1989.
Husain
Nov. 2 "Flash Memory Goes Mainstream", Brian Dipert and Lou Hebert, IEEE Spectrum, October 1993, pp. 48-52.

"Filing in a Flash", James Eldridge, IEEE Spectrum, October 1993, pp. 53-54.

Related Reading: 		Keckler

Physical and Electrical Considerations:

Packaging
Nov. 4 "Large Chip vs. MCM for a High-Performance System", Evan E. Davidson, IEEE Micro, July/August 1998, pp. 33-41.

Related Reading:
  • "Future System-on-Silicon LSI Chips", Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, and Hikotaro Itani, IEEE Micro, July/August 1998, pp. 17-22.
  • "VLSI, MCM, and WSI: A Design Comparison", Earl E. Schwartzlander, IEEE Design and Test, July-September 1998, pp. 28-34.
Shinghal
Power
Nov. 9 "Low Power Design Issues", Mark Horowitz, Slides presented at the 1998 Power Driven Microarchitecture Workshop, pp. 1-48.

"Low-Power Digital Design", M. Horowitz, T. Indermaur, and R. Gonzalez, Proceedings of the 1994 IEEE Symposium on Low Power Electronics, October 1994, pp. 10-12.

"Energy Dissipation in General Purpose Processors", Ricardo Gonzalez and Mark Horowitz, Proceedings of the 1994 IEEE Symposium on Low Power Electronics, October 1994, pp. 9-11.

Related Reading:
  • "A Low Power Switching Power Supply for Self-Clocked Systems", Gu-Yeon Wei and Mark Horowitz, Proceedings of the 1996 IEEE Symposium on Low Power Electronics, August 1996, pp. 313-317.
  • "Energy Dissipation in General Purpose Microprocessors", Ricardo Gonzalez and Mark Horowitz, IEEE Journal of Solid State Circuits, September 1996, vol. 31:9, pp. 1277-1284.
  • "Low-Power CMOS Digital Design", Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Broderson, IEEE Journal of Solid State Circuits, April 1992, vol. 27:4, pp. 473-484.
Bhargava, Shen
Nov. 11 "Dynamic Power Management for Microprocessors: A Case Study", Vivek Tiwari, Ryan Donnelly, Sharad Malik, and Ricardo Gonzalez, Proceedings fo the 10th International Conference on VLSI Design, Jnauary 1997, pp. 185-192.

Related Reading:
  • "A history of low power electronics: how it began and where it's headed", James D. Meindl, Proceedings of 1997 International Symposium on Low Power Electronics and Design, Monterey, CA, August 1997, pp. 149-151.
  • "Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design", Vivek Tiwari, Sharad Malik, and Pranav Ashar, Proceedings of the 1995 International Symposium on Low Power Design, pp. 221-226.
  • "The Design of a High Performance Low Power Microprocessor", Dan Dobberpuhl, Proceedings of 1996 International Symposium on Low Power Electronics and Design, pp. 11-16.
Kothari
Nov. 16 "An Architectural Level Power Estimator", Rita Yu Chen, Mary Jane Irwin, and Raminder S. Bajwa, Proceedings of the 1998 Power Driven Microarchitecture Workshop, pp. 87-91.

"Instruction Scheduling for Low Power Dissipation in High Performance Microprocessors", Mark C. Toburen, Thomas M. Conte, and Matt Reilly,Proceedings of the 1998 Power Driven Microarchitecture Workshop, pp. 14-19.

Related Reading:
  • "High-Level Power Estimation", Paul Landman, Proceedings of 1996 International Symposium on Low Power Electronics and Design Monterey, CA, August 1996, pp. 29-35.
  • "Power analysis and low-power scheduling techniques for embedded DSP software", Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, and Masahiro Fujita, Proceedings of the Eighth International Symposium on System Synthesis, September 1995, pp. 110-15.
  • "Low Power Architecture Design and Compilation Techniques for High-Performance Processors", Ching-Long Su, Chi-Ying Tsui, and Alvin M. Despain, Proceedings of COMPCON, March 1994, pp. 489-98.
Ferris, Shen
Off-Chip Communication
Nov. 18 "Starfire: Extending the SMP Envelope", Alan Charlesworth, IEEE Micro, January/February 1998, pp. 39-49.

Related Reading:
  • "The SGI Origin: A ccNUMA Highly Scalable Server", James Laudon and Dan Lenoski, Proceedings of the 1997 International Symposium on Computer Architecture, June 1997, pp. 241-251.
  • "The Mercury Interconnect Architecture: A Cost-effective Infrastructure for High-performance Servers", Wolf-Dietrich Weber, Stephen Gold, Pat Helland, Takeshi Shimizu, Thomas Wicki, and Winfried Wilcke, Proceedings of the 1997 International Symposium on Computer Architecture, June 1997, pp. 98-107.
 Keckler
Nov. 23 "High-Performance Bidirectional Signalling in VLSI Systems", Larry R. Dennison, Whay S. Lee, and William J. Dally, Proceedings of the Symposium on Integrated Systems, March 1993, pp. 300-319.

Related Reading:
  • "Simultaneous Bidirectional Switching for IC Systems", Kevin Lam, Larry R. Dennison, and William J. Dally, Proceedings of the 1990 IEEE International Conference on Computer Design, September 1990, pp. 430-433.
  • "A 900Mb/s Bidirectional Switching Scheme", Randy Mooney, Charles Dike, and Shekhar Borkar, Proceedings of the 1995 International Solid-State Circuits Conference, pp. 38-39.
  • "A Novel Memory Bus Driver/Receiver Architecture for High Throughput", Gregory E. Beers and Lizy K. John, Proceedings of the 11th International Conference on VLSI Design, January 1998, pp. 259-264.
Srinivasan
Nov. 25 Project Presentations
Project Reports Due
Nov. 30 Class Cancelled
Dec. 2 TBA Keckler

Supplementary Reading

  • "The Effervescent Years: A Retrospective", Henry Tropp, IEEE Spectrum, February 1974, pp. 70-81.

  • "A Participants Perspective", R. Gary Daniels, IEEE Micro, December 1996, vol. 16:6, pp. 21-31.

  • "Lithography and the Future of Moore's Law", Gordon E. Moore, Proceedings of the SPIE 1995, vol. 2440, pp. 2-17.

  • "Physical Technology for VLSI Systems", R. Hannemann, Proceedings of the 1986 IEEE International Conference on Computer Design, pp. 48--53.

  • "A 600MHz Superscalar RISC Microprocessor with Out-Of-Order Execution", Bruce A. Gieseke, et. al. Proceedings of the 1997 IEEE International Solid-State Circuits Conference, pp. 176-177, 451, (Note: Alpha 21264).

  • "A 480MHz RISC Microprocessor in a 0.12um Leff CMOS Technology with Copper Interconnects", N. Rohrer, et. al. Proceedings of the 1998 IEEE International Solid-State Circuits Conference, pp. 240-241 (Note: IBM technology demonstration).

  • "Symbolics Architecture", David A. Moon, IEEE Computer, vol. 20:1, January 1997, pp. 43-52.

  • "Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture", David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, and Wen-mei W. Hwu, Proceedings of the International Symposium on Computer Architecture, July 1998, pp. 227-237.

  • "Designing for a Gigahertz", H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel A. Silberman, Jeffrey L. Burns, Stephen D. Posluszny, and Osamu Takahashi, IEEE Micro, May/June 1998, pp. 66-74.

  • "A 1.0GHz Single-Issue 64b PowerPC Integer Processor", J. Silberman, N. Aoki, D. Boerstler, J. Burns, S. Dhong, A. Essbaum, U. Ghoshal, D. Heidel, P. Hofstee, K. Lee, D. Meltzer, H. Ngo, K. Nowka, S. Posluszny, O. Takahashi, I. Vo, and B. Zonc, Proceedings of the 1998 International Solid State Circuits Conference, pp. 230-231.

  • "Low Load Latency Through Sum-Addressed Memory (SAM)", William L. Lynch, Gary Lauterbach, and Joseph I. Chamdani, Proceedings of the International Symposium on Computer Architecture, June 1998, pp. pp. 369-377.

  • "M32R/D-Integrating DRAM and Microprocessor", Yasuhiro Nunomura, Toru Shimizu, and Osami Tomisawa, IEEE Micro, November/December 1997, pp. 40-48.

  • "Rewritable Optical Disk Drive Technology", P. Asthana, B.I. Finkelstein, and A.A. Fennema, IBM Journal of Research and Development, September 1996, vol. 40:5, pp. 543-558.

  • "Flip-Chip Soldering to Bare Copper Circuits", Anthony P. Ingraham, Jack M. McCreary, and Jack A. Varcoe, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 13:4, December 1990, pp. 656-660.

  • "Future System-on-Silicon LSI Chips", Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, and Hikotaro Itani, IEEE Micro, July/August 1998, pp. 17-22.

  • "The Cray Y-MP - A VLSI Supercomputer", S. Bowen, Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 21-23.

  • "The NEC SX Supercomputer Technology", Toshihiko Watari, Proceedings of the 1986 IEEE International Conference on Computer Design, pp. 54-57.

  • "High-Speed Electrical Signalling: Overview and Limitations", Mark Horowitz, Chih-Kong Ken Yang, and Stefanos Sidiropoulos, IEEE Micro, January/February 1998, pp. 12-24.