The design that we loaded. The contents of the design have
been only minimally transformed (e.g., to add declarations for
implicit wires). They meant to closely reflect the actual
source code as it occurs on the disk.
Alist mapping file names to their original, unmodified
contents as strings. This can be useful for interactively
looking at module definitions, but takes some memory. You can
control whether a filemap is generated in your vl-loadconfig-p.
