Four-valued semantics for a wired or.
(4v-wor a b) returns:
We use this to model what happens when multiple signals are connected in a wired-or arrangement.
The full truth table is shown below. It intentionally corresponds to the Verilog semantics for wired ors (Section 4.6.2 of the Verilog specification).
| F T X Z | -----+------------------+ F | F T X F | T | T T T T | X | X T X X | Z | F T X Z | -----+------------------+
Function:
(defun 4v-wor (a b) (declare (xargs :guard t)) (mbe :logic (4vcases a (t (4vt)) (f (4vcases b (z (4vf)) (& (4v-fix b)))) (z (4v-fix b)) (& (4vcases b (t (4vt)) (& (4vx))))) :exec (cond ((eq a (4vt)) (4vt)) ((eq b (4vt)) (4vt)) ((eq a (4vf)) (if (or (eq b (4vf)) (eq b (4vz))) (4vf) (4vx))) ((eq a (4vz)) (if (or (eq b (4vf)) (eq b (4vz))) b (4vx))) (t (4vx)))))
Theorem:
(defthm 4v-wor-truth-table (and (equal (4v-wor (4vf) (4vf)) (4vf)) (equal (4v-wor (4vf) (4vt)) (4vt)) (equal (4v-wor (4vf) (4vx)) (4vx)) (equal (4v-wor (4vf) (4vz)) (4vf)) (equal (4v-wor (4vt) (4vf)) (4vt)) (equal (4v-wor (4vt) (4vt)) (4vt)) (equal (4v-wor (4vt) (4vx)) (4vt)) (equal (4v-wor (4vt) (4vz)) (4vt)) (equal (4v-wor (4vx) (4vf)) (4vx)) (equal (4v-wor (4vx) (4vt)) (4vt)) (equal (4v-wor (4vx) (4vx)) (4vx)) (equal (4v-wor (4vx) (4vz)) (4vx)) (equal (4v-wor (4vz) (4vf)) (4vf)) (equal (4v-wor (4vz) (4vt)) (4vt)) (equal (4v-wor (4vz) (4vx)) (4vx)) (equal (4v-wor (4vz) (4vz)) (4vz))) :rule-classes nil)